28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 182

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Figure 7-14. EBUS Write/Read Transactions, Motorola-Style
28478-DSH-002-E
GENERAL NOTE:
1. BG* assertion depends on the external bus arbiter. While BG* and BR* are both deasserted, MUSYCC places shared EBUS signals
2. One ECLK cycle after BG* assertion, MUSYCC outputs valid command bus signals: EBE, AS*, R/WR*, and DS*.
3. Two ECLK cycles after BG* assertion, MUSYCC outputs valid EAD address signals. BGACK* assertion occurs three ECLK cycles after
4. ALAPSE inserts a variable number of ECLK cycles to extend AS* high pulse width and EAD address interval.
5. EAD address remains valid for one ECLK cycle after AS* falling edge. During a write transaction, MUSYCC asserts R/WR* and
6. ELAPSE inserts a variable number of ECLK cycles to extend DS* low pulse width and EAD data interval. Read data inputs are
7. EAD write data, EBE, R/WR*, and AS* signals remain valid for one ECLK cycle after BGACK* and DS* are deasserted.
8. One ECLK cycle after BGACK* deassertion, the BR* output is deasserted and the bus is parked (command bus deasserted, EAD
9. Command bus is unparked (three-stated) one ECLK after BG* deassertion; two different unpark phases are shown, indicating the
10. BLAPSE inserts a variable number of ECLK cycles to extend BR* deassertion interval until the next bus request.
in high impedance (three-state, as shown by dashed lines).
BG* and BR* are both asserted.
outputs valid EAD write data one ECLK prior to DS* assertion. During a read transaction, EAD data lines are input.
sampled on ECLK rising edge coincident with DS* deassertion.
three-state). The bus parked state ends when the external bus arbiter deasserts BG*.
dependence on BG* deassertion. If BG* remained asserted until the next bus request, then command bus remains parked until one
ECLK following the next BR* assertion. Warning: Whenever BG* is deasserted, all shared EBUS signals are forced to three-state
after one ECLK cycle, regardless of whether the EBUS transaction was completed. MUSYCC will not reissue or repeat such an
aborted transaction.
8478_036
R/WR* (write)
R/WR* (read)
See Notes
EAD[31:0]
EBE[3:0]*
Preliminary Information / Mindspeed Proprietary and Confidential
BGACK*
ECLK
BG*
BR*
DS*
AS*
Mindspeed Technologies
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2
Byte Enables from PCI Data Phase
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ALAPSE = 0
Address
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Electrical and Mechanical Specifications
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®
ELAPSE = 0
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Data
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BLAPSE = 0
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