28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 50

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Register 5–14, Address 14h–38h
Table 2-8.
Register 15, Address 3Ch
Table 2-9.
2.2.2
MUSYCC, a multifunction PCI device, provides the necessary configuration space allowing a PCI bus or system
controller to query and configure the host interface of MUSYCC as a PCI device. PCI configuration space consists
of a device-independent header region (64 bytes) and a device-dependent header region (192 bytes). MUSYCC
provides the 64-byte device-independent header section only. Access to the device-dependent header region
results in 0s being read, and no effect on writes.
There are three types of registers available in MUSYCC:
1. Read-Only (RO)—Returns a fixed bit pattern if the register is used, or a 0 if the register is unused or reserved.
2. Read-Resettable (RR)—Can be reset to 0 by writing a 1 to the register.
3. Read/Write (RW)—Retains the value last written to it.
MUSYCC’s Function 1 Configuration Space has 16 dword registers.
registers.
28478-DSH-002-E
FOOTNOTE:
Field
Field
31:24
23:16
31:0
15:8
Bit
Bit
7:0
Maximum Latency
Minimum Grant
Interrupt Line
An active-low signal is denoted by a trailing asterisk (*).
Reserved
Interrupt Pin
Registers 5–14, Addresses 14h–38h
Register 15, Address 3Ch
Function 1 Expansion Bus Bridge, PCI Slave
Name
Name
Preliminary Information / Mindspeed Proprietary and Confidential
Reset
Value
Reset
Value
Mindspeed Technologies
0Fh
01b
0
0
0
Type
Type
RW
RO
RO
RO
RO
Unused.
Specifies how quickly MUSYCC needs to gain access to the PCI bus. The
value is specified in 0.25 µs increments and assumes a 33 MHz clock. 0Fh
means MUSYCC needs to gain access to the PCI bus every 130 PCI clock
cycles, expressed as 3.75 µs in this register for 33 MHz PCI and 1.87 µs for
66 MHz PCI.
This value specifies, in 0.25 µs increments, the minimum burst period
MUSYCC needs. MUSYCC does not have any special MIN_GNT
requirements. In general, the more channels MUSYCC has active, the worse
the bus latency and the shorter the burst cycle.
Defines which PCI interrupt pin Function 0 uses. 01h means MUSYCC uses
pin INTA* for HDLC controller interrupts.
Communicates interrupt line routing. System initialization software will write
a value to this register indicating which host interrupt controller input is
connected to MUSYCC’s INTA* pin.
®
Tables 2-10
Description
Description
through
2-16
describe these
Host Interface
37