28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 16

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Figures 1-2
Figure 1-2.
28478-DSH-002-E
8478 002
and
Detailed System Block Diagram
CBE[3:0]*
DEVSEL*
FRAME*
AD[31:0]
1-3
SERR*
IDSEL*
M66EN
PRST*
PERR*
TRDY*
STOP*
TEN*
IRDY*
TMS
TDO
PCLK
INTB*
INTA*
TCK
GNT*
REQ*
PAR*
TDI
illustrate detailed system block diagrams and a sample application.
Configuration
Configuration
Configuration
Host Interface
[Function 0]
[Function 1]
Preliminary Information / Mindspeed Proprietary and Confidential
Registers
Interface
Device
Space
Space
PCI
PCI
PCI
Control
Scan
Data
Mindspeed Technologies
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Serial Interface Channel Group 0
Serial Interface Channel Group 1
Serial Interface Channel Group 2
Serial Interface Channel Group 3
Serial Interface Channel Group 4
Serial Interface Channel Group 5
Serial Interface Channel Group 6
Serial Interface Channel Group 7
Boundary Scan and Test Access
Tx/Rx-DMAC
Tx/Rx-DMAC
Tx/Rx-DMAC
Tx/Rx-DMAC
Tx/Rx-DMAC
Tx/Rx-DMAC
Tx/Rx-DMAC
Tx/Rx-DMAC
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Expansion Bus Interface
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
Tx/Rx-BLP
Tx/Rx-BLP
Tx/Rx-BLP
Tx/Rx-BLP
Tx/Rx-BLP
Tx/Rx-BLP
Tx/Rx-BLP
Tx/Rx-BLP
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Processor
®
Bit-Level
Bit-Level
Bit-Level
Bit-Level
Bit-Level
Bit-Level
Bit-Level
Bit-Level
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Port
Port
Port
Port
Port
Port
Port
Port
WR* (R/WR*)
HOLD (BR*)
HLDA (BG*)
SCAN_EN
EAD[31:0]*
RD* (DS*)
EBE[3:0]*
System Description
BGACK*
RSYNC0
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
TSYNC0
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
EINT*
ROOF0
ROOF1
ROOF2
ROOF3
ROOF4
ROOF5
ROOF6
ROOF7
ECLK
RCLK0
RDAT0
TDAT0
RCLK1
RDAT1
TDAT1
RCLK2
RDAT2
TDAT2
RCLK3
RDAT3
TDAT3
RCLK4
RDAT4
TDAT4
RCLK5
RDAT5
TDAT5
RCLK6
RDAT6
TDAT6
RCLK7
RDAT7
TDAT7
ALE*
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TM0
TM1
3