28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 40

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 1-4.
28478-DSH-002-E
FOOTNOTE:
(1)
(2)
(3)
(4)
(5)
These pins have internal pullups and may be left open by the system designer.
VDDc Pin Numbers: 27, 77, 132, 185
VDDi Pin Numbers: 13, 67, 118, 171
VDDo Pin Numbers: 42, 63, 81, 95, 110, 147, 164, 181, 201
VGG Pin Numbers: 52, 156
VSS Pin Numbers: 14, 28, 53, 68, 78, 119, 133, 157, 172, 186
VSSo Pin Numbers: 44, 55, 64, 73, 82, 89, 96, 104, 111, 137, 148, 153, 165, 175, 182, 191, 202
An active low signal is denoted by a trailing asterisk (*).
These pins have internal pulldowns and may be left open by the system designer.
35
36
37
38
39
112–114
(2)
(3)
Pin No.
MQFP
CN8478 Hardware Signal Definitions (6 of 6)
TM[0]
TCK
TRST*
TMS
TDO
TDI
TM[1]
TM[2]
VDDc
VDDi
VDDo
VGG
VSS
VSSo
Pin Label
(1)
(3)
(1)
(3)
(5)
(5)
(5)
(1)
Preliminary Information / Mindspeed Proprietary and Confidential
JTAG Clock
JTAG Reset
JTAG Mode Select
JTAG Data Output
JTAG Data Input
Test Mode
Power
Ground
Signal Name
Mindspeed Technologies
t/s O
I/O
—
—
I
I
I
I
I
Clock in the TDI and TMS signals and clock out TDO signal.
An active-low input that resets the JTAG state machine. This pin should be
pulled low in normal operation.
The test signal input decoded by the TAP controller to control test
operations.
The test signal that transmits serial test instructions and tests data.
The test signal that receives serial test instructions and tests data.
Encodes test modes.
19 pins are provided for power. Four VDDc (core), four VDDi (input), nine
VDDo (output), and two VGG (5 V-tolerant supply). The VDDc require 2.5
V +/- 5%, the VDDi and VDDo require 3.3 V +/- 5%, and the VGG require 5
V +/- 5%. The recommended power ramp sequence is VDDi and VDDo
together, then VDDc at t = 0
27 pins are provided for ground, 0 V DC. 10 VSS (core and input) and 17
VSSo (output).
TM[0]
0
1
TM[1]
®
0
1
TM[2]
0
1
+
. VGG can be powered at any time.
Normal Operation. Tie to ground.
All outputs three-stated.
Definition
27