28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 65

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 3-2.
3.1.10
The HOLD and HLDA (Intel style) or BR* and BG* (Motorola style) signal lines are used by MUSYCC to arbitrate
for the EBUS.
For Intel-style interfaces, the arbitration protocol is as follows (refer to
Transactions,
1. MUSYCC three-states EAD[31:0], EBE*[3:0]. WR*, RD*, and ALE*.
2. MUSYCC requires EBUS access and asserts HOLD.
3. MUSYCC checks for HLDA assertion by bus arbiter.
4. If HLDA is deasserted, MUSYCC waits for the HLDA signal to become asserted before continuing the EBUS
5. If HLDA is asserted, MUSYCC continues with the EBUS access because it has control of the EBUS.
6. MUSYCC drives EAD[31:0], EBE*[3:0], WR*, RD*, and ALE*.
7. MUSYCC completes EBUS access and deasserts HOLD.
8. Bus arbiter deasserts HLDA shortly thereafter.
9. MUSYCC three-states EAD[31:0], EBE*[3:0]. WR*, RD*, and ALE*.
For Motorola-style interfaces, the arbitration protocol is as follows (refer to
Transactions,
1. MUSYCC three-states EAD[31:0], EBE*[3:0]. R/WR*, DS*, and AS*.
2. MUSYCC requires EBUS access and asserts BR*.
3. MUSYCC checks for BG* assertion by bus arbiter.
4. If BG* is deasserted, MUSYCC waits for the BG* signal to become asserted before continuing the EBUS
5. If BG* is asserted, MUSYCC continues with the EBUS access as it has control of the EBUS.
28478-DSH-002-E
AS*
DS*
R/WR*
BR*
BG*
BGACK*
FOOTNOTE:
operation.
operation.
Signal
An active low signal is denoted by a trailing asterisk (*).
Motorola Protocol Signal
Intel-Style):
Motorola-Style):
Arbitration
Address Strobe
Data Strobe
Read/Write
Bus Request
Bus Grant
Bus Grant Acknowledge
Preliminary Information / Mindspeed Proprietary and Confidential
Description
Mindspeed Technologies
Driven low by MUSYCC to indicate that the address lines contain a valid address. This
signal remains asserted for the duration of the access cycle.
Strobed low by MUSYCC to enable data reads or data writes for the addressed device.
MUSYCC. This signal determines the meaning (read or write) of DS*.
Asserted low by MUSYCC when it requests the EBUS from a bus arbiter.
Asserted low by bus arbiter in response to BR* signal assertion. Remains asserted
until after the BR* signal is deasserted. If the EBUS is connected and there are no bus
arbiters on the EBUS, this signal must be asserted low at all times.
Asserted low by MUSYCC when it detects BGACK* currently deasserted. As this signal
is asserted, MUSYCC begins the EBUS access cycle. After the cycle is finished, this
signal is deasserted indicating to the bus arbiter that MUSYCC has released the EBUS.
Held high throughout read operation and held low throughout write operation by
®
Figure 7-13, EBUS Write/Read
Figure 7-14, EBUS Write/Read
Interpretation
Expansion Bus (EBUS)
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