28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 81

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

If the buffer space is evenly divided across 16 channels, the BUFFLOC and BUFFLEN specification would be as
listed in
Table 4-5.
4.7.2
As a receive channel is activated, MUSYCC reads in descriptors from shared memory and prepares Rx-BLP and
Rx-DMAC to service incoming serial data accordingly, assuming all configurations are proper, and incoming data
can be written to shared memory.
Upon channel activation, the receiver starts storing received data into a BUFFLEN+1 size of FIFO, starting at
BUFFLOC offset in the FIFO buffer area. As this buffer fills, the BLP instructs the DMAC to start a PCI data transfer
cycle to shared memory of the FIFO buffer contents and simultaneously starts filling another BUFFLEN+1 size of
FIFO buffer from the serial port. Generally, half the FIFO buffer space for a channel is used for serial port data
reception, and half for shared memory data transfers.
The DMAC-initiated PCI transfer cycle requires MUSYCC to arbitrate for the PCI bus, initiate a master write to
shared memory over the PCI bus, and conclude the transfer by releasing the PCI bus. MUSYCC transfers data
autonomously and always attempts to burst data to the PCI.
4.7.3
When a transmit channel is activated, MUSYCC reads in descriptors from shared memory and prepares Tx-BLP
and Tx-DMAC to service outgoing serial data, assuming all configurations are proper, and outgoing data can be
read from shared memory.
Upon channel activation, the transmitter initiates a PCI data transfer cycle from shared memory of data to be output
to the serial port. As the DMAC receives data over the PCI, it forwards it to the BLP which fills a BUFFLEN+1 size
of FIFO starting at BUFFLOC offset in the FIFO area. Generally, half the FIFO space for a channel is used for
serial port data transmission and half for shared memory data transfers.
The DMAC-initiated PCI transfer cycle requires that MUSYCC arbitrate for the PCI bus, initiate a master read from
shared memory over the PCI bus, and conclude the transfer by releasing the PCI bus. MUSYCC transfers data
autonomously and always attempts to burst data from the PCI.
28478-DSH-002-E
FOOTNOTE:
(1)
(2)
Assuming all channels within a group operate at the same bit rate, BUFFLEN = [(Total dwords
BUFFLEN values larger than 1Fh do not increase the PCI burst length. BUFFLEN determines the number of dwords burst during a PCI
read/write operation to fill or flush the internal data buffer. For example, BUFFLEN = 1Fh specifies a burst length of 32 dwords.
Table
Channel
Number
15
...
0
1
2
4-5, for 16 channels with subchannel buffer allocation.
Example of 16-Channel without Subchanneling Buffer Allocation (Receive or Transmit)
Receiving Bit Stream
Transmitting Bit Stream
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
(dword Offset from Start of
Fixed Data Buffer)
BUFFLOC
60
...
0
4
8
Within Channel Descriptor
®
÷
Number of Channels)
BUFFLEN
3
...
3
3
3
(2)
Serial Interface
(1)
÷
2]–1.
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