28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 52

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Register 1, Address 04h
The Status register records status information for PCI bus-related events. The Command register provides coarse
control to generate and respond to PCI commands.
At reset, MUSYCC sets the bits in this register to 0. This means MUSYCC is logically disconnected from the PCI
bus for all cycle types except configuration read and configuration write cycles.
Table 2-11.
28478-DSH-002-E
FOOTNOTE:
Field
26:25
20:16
15:7
Bit
5:2
31
30
29
28
27
24
23
22
21
6
1
0
Status
Command
An active-low signal is denoted by a trailing asterisk (*).
Register 1, Address 04h
Name
Preliminary Information / Mindspeed Proprietary and Confidential
Reset
Value
Mindspeed Technologies
01b
01b
01b
0
0
0
0
0
0
0
0
0
0
0
0
0
Type
RW
RW
RR
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Detected parity error. This bit is set by MUSYCC whenever it detects a parity
error on a data phase.
Unused.
Unused.
Unused.
Unused.
DEVSEL* timing. Indicates MUSYCC is a medium-speed device. This means
the longest time it will take MUSYCC to return DEVSEL* when the EBUS is
the target is 3 clock cycles.
Unused.
Fast back-to-back capable. Indicates that when the EBUS is a target, it is
capable of accepting fast back-to-back transactions when the transactions
are not to the same agent.
Unused.
Indicates the device is 66 MHz capable. This bit is set by Revision C and later
devices.
Unused.
Unused.
Parity error response.
on a cycle with Function 1 as the target.
Unused.
Memory Space access control.
access cycles.
I/O space accesses. MUSYCC does not contain any I/O space registers.
This bit controls MUSYCC’s Function 1 response to parity errors.
If 1, MUSYCC will take normal action when a parity error is detected
If 0, MUSYCC will ignore parity errors.
If 1, enables MUSYCC to respond to Function 1 memory space
If 0, disables MUSYCC’s response.
®
Description
Host Interface
39