28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 46

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Register 1, Address 04h
The Status register records status information for PCI bus related events. The Command register provides coarse
control to generate and respond to PCI commands.
At reset, MUSYCC sets the bits in this register to 0, meaning MUSYCC is logically disconnected from the PCI bus
for all cycle types except configuration read and configuration write cycles.
Table 2-4.
28478-DSH-002-E
Field
26:25
20:16
Bit
31
30
29
28
27
24
23
22
21
Register 1, Address 04h (1 of 2)
Name
Status
Preliminary Information / Mindspeed Proprietary and Confidential
Reset
Value
Mindspeed Technologies
01b
1b
0
0
0
0
0
0
0
0
I
Type
RR
RR
RR
RR
RO
RO
RR
RO
RO
RO
RO
Detected Parity Error. This bit is set by MUSYCC whenever it detects a parity
error on a data phase when MUSYCC is a target, even if parity error response
is disabled.
Detected System Error. This bit is set by MUSYCC whenever it asserts
SERR*.
Received Master Abort. This bit is set by MUSYCC whenever a MUSYCC-
initiated cycle is terminated with master-abort.
Received Target Abort. MUSYCC sets this bit when a MUSYCC-initiated cycle
is terminated by a target-abort.
Unused.
DEVSEL* Timing. Indicates MUSYCC is a medium-speed PCI device. This
means the longest time it will take MUSYCC to return DEVSEL* when it is a
target of 3 clock cycles.
Data Parity Detected. MUSYCC sets this bit when three conditions are met:
Fast Back-to-Back Capable. Read Only. Indicates that when MUSYCC is a
target, it is capable of accepting fast back-to-back transactions when the
transactions are not to the same agent.
Unused.
Indicates the device is 66 MHz capable. This bit is set by Revision C and later
devices.
Unused.
1. MUSYCC asserts PERR* or observes PERR*.
2. MUSYCC is the master for that transaction.
3. The Parity Error Response bit in this register is set.
®
Description
Host Interface
33