28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 98

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

5.2.2.4
The memory protection function is not implemented. This function must be disabled by clearing the PROTENBL bit
in the Memory Protection Descriptor.
Descriptor.
Table 5-11.
5.2.2.5
The Port Configuration Descriptor defines how MUSYCC interprets and synchronizes the transmit and receive bit
streams associated with a port. There is one descriptor per port; therefore, the descriptor is used for both transmit
and receive directions for a single port.
Table 5-12
Table 5-12.
28478-DSH-002-E
Field
Field
30:28
27:16
15:12
31:10
11:0
Bit
Bit
31
9
8
7
details the Port Configuration Descriptor.
PROTLO[11:0]
RSYNC_EDGE
PROTHI[11:0]
ROOF_EDGE
PROTENBL
Memory Protection Descriptor
Port Configuration Descriptor (1 of 2)
Name
Name
TRITX
RSVD
RSVD
RSVD
NOTE:
Memory Protection Descriptor
Port Configuration Descriptor
Preliminary Information / Mindspeed Proprietary and Confidential
Identically to the used port descriptor. That is, if PORTMAP=1, then the group 1/port 1
descriptor must be bit-for-bit identical with the group 0/port 0 descriptor; and, the group 3/
port 3 descriptor must be bit-for-bit identical with the group 2/port 2 descriptor. In the case
of PORTMAP=2, then the group 1, 2, and 3 descriptors must be bit-for-bit identical with the
group 0/port 0 descriptor.
Value
Value
—
—
0
1
0
0
0
0
1
0
1
0
1
Memory Protection Disabled.
Memory Protection Enabled. Not supported.
Reserved.
Memory Protection High Address. Upper 12 bits (inclusive) of address for highest memory location
under protection.
Reserved.
Memory Protection Low Address. Upper 12 bits (inclusive) of the address for lowest memory location
under protection.
Reserved.
Transmit Three-state Enabled. When a channel group is enabled, but a time slot within the group is
not mapped via the Time Slot Map, the transmitter three-states the output data signal.
Transmit Three-State Disabled. When a channel group is enabled, but a time slot within the group is
not mapped via the Time Slot Map, the transmitter outputs a logic 1 on the output data signal.
Receiver Out of Frame—Falling Edge. ROOF input sampled in on falling edge of RCLK.
Receiver Out of Frame—Rising Edge.
Receiver Frame Synchronization—Falling Edge. RSYNC input sampled in on falling edge of RCLK.
Receiver Frame Synchronization—Rising Edge.
Table 5-11
Mindspeed Technologies
lists the bit field and description of the Memory Protection
®
Description
Description
Memory Organization
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