28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 58

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 2-17.
The predictable worst case time MUSYCC must wait for the bus in a system with k masters with equal latency
timers is [k
If one MUSYCC is configured with all 256 channels active, and receiving and transmitting at 64 kbps, it must
maintain a data rate of 16 Mbps across the PCI bus. Therefore:
•
With 32 bits in each dword, the data rate in kilo dwords per second (kdwps) is:
•
The 16-clock rule (PCI Local Bus Specification, Revision 2.1) requires that a single access device must complete
the access cycle within 16 clock cycles of the FRAME* signal being asserted. For devices capable of burst-mode,
the 16-clock rule applies to the completion of the first data cycle.
2.2.6.2
Assuming the worst case scenario where the system allows only single dword access, even a burst-mode device
such as MUSYCC must relinquish the PCI bus within 16 clock cycles from receiving the bus. Using this scenario,
the calculations continue as follows:
•
•
•
•
•
28478-DSH-002-E
+(T + 8) or [16 + (n - 1) x 8]
whichever is smaller
— Host has bus —
+(T + 8) or [16 + (n - 1) x 8]
whichever is smaller
— MUSYCC0 has bus —
+(T + 8) or [16 + (n - 1) x 8]
whichever is smaller
— MUSYCC1 has bus —
FOOTNOTE:
256 channels
32,768 kbps / (32 bits/dword) = 1,024 kdwps
The time per dword would be:
1 dword / 1,024 kdwps = 0.98 µs per dword
Assuming a PCI bus rate of 33 MHz, the time per clock cycle would be:
1 cycle / 33 MHz = 30.303 ns per clock cycle
Assuming a PCI bus rate of 66 MHz, the time per clock cycle would be:
1 cycle / 66 MHz = 15.152 ns per clock cycle
To get the number of clock cycles per dword:
0.98 µs per dword / 0.0303 µs per clock cycle = 33 PCI clock cycles per dword
To get the number of clock cycles per dword:
0.98 µs per dword / 0.0152 µs per clock cycle = 66 PCI clock cycles per dword
PCI Clock Increment
An active low signal is denoted by a trailing asterisk (*).
x
(T + 8)].
PCI Latency Example (2 of 2)
x
Latency Computation—Single Dword Access
(64 kbps Rx + 64 kbps Tx) = 32,768 kbps
Preliminary Information / Mindspeed Proprietary and Confidential
This is the bus acquisition latency time—the amount of time the next requestor must wait for the bus because of
current master, the host.
During this time, assume the host loses its GNT* just +1 clock cycle into its acquisition and MUSYCC0 receives
the GNT* +1 into this time.
The host’s first data phase must finish within 16 PCI clock cycles, and subsequent data phases must finish within
8 cycles each. Therefore, 16 + (n - 1)
phases (n dword burst), assuming the host’s access finishes before its latency timer expires.
As the cycle finishes, the host relinquishes the bus, and one clock cycle later, MUSYCC0 gets the GNT* and
subsequently asserts its FRAME* to start the access cycle.
MUSYCC0 finishes with the bus, and MUSYCC1 has it on the next clock cycle. During this time, MUSYCC0 loses
its GNT*, and MUSYCC1 receives its GNT*. MUSYCC0 behaves similarly to the host above.
MUSYCC1 finishes with the bus, and MUSYCC2 has it on the next clock cycle. During this time, MUSYCC1 loses
its GNT*, and MUSYCC2 receives its GNT*. MUSYCC1 behaves similarly to the host above.
Mindspeed Technologies
x
8 clock cycles is how long the host will need the bus to execute n data
Bus Activity
®
Host Interface
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