28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 55

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

2.2.3
MUSYCC resets all internal functions when it detects the assertion of the PRST* signal line. Upon reset, the
following occurs:
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2.2.4
After a hardware reset, the PCI configuration space within MUSYCC needs to be configured by the host with the
following information:
For Function 0:
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For Function 1:
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Function 0 provides services to the serial interfaces in MUSYCC; Function 1 provides services to the EBUS
interface in MUSYCC.
After the configuration spaces are configured, MUSYCC can master the PCI bus or provide slave-mode access to
the host.
2.2.5
The agent driving the AD[31:0] signals during any bus phase must also drive the even parity signal (PAR). PAR is
driven one clock after AD[31:0] has been driven as follows:
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PAR provides even parity across the AD[31:0] and CBE[3:0]* signal lines. The agent receiving the data must assert
PERR* if it detects a parity error, provided its Parity Error Response enable bit is set.
28478-DSH-002-E
All PCI output signals go to three-state immediately and asynchronously with respect to the PCI clock input,
PCLK.
All EBUS output signals go to three-state immediately and asynchronously with respect to the EBUS clock
output, ECLK.
All writable register bits are set to 0.
All PCI data transfers terminate immediately.
All serial data transfers terminate immediately.
MUSYCC disables and responds only to PCI configuration cycles.
Base address register
Fast back-to-back enable/disable
SERR* signal driver enable/disable
Parity error response enable/disable
Bus mastering enable/disable
Memory space access enable/disable
Base address register
Parity error response enable/disable
Memory space access enable/disable
Address phase: master always drives PAR one clock after address phase.
Read data phase: target always drives PAR one clock after read data phase.
Write data phase: master always drives PAR one clock after write data phase.
PCI Reset
Host Interface
PCI Bus Parity
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Host Interface
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