28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 63

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

3.1.4
When a device connected to the EBUS drives the EINT* signal, MUSYCC carries this signal through to the PCI
interrupt line, INTB*. Thus, peripheral devices can interrupt the host processor.
In MUSYCC’s Function 1 PCI Configuration Space (the EBUS function), the Interrupt Pin bit field indicates that the
INTB* PCI interrupt be asserted for interrupts sourced by devices connected to the EBUS (see
16, Register 15, Address
initialization software to indicate which host interrupt controller input pin is to be connected to MUSYCC’s INTB*
pin.
3.1.5
MUSYCC can extend the duration the address bits are valid for any EBUS address phase by specifying a value
from 0–3 in ALAPSE bit field (refer to
additional ECLK periods the address bits remain asserted. That is, a value of 0 specifies the address remains
asserted for one ECLK period, and a value of 3 specifies the address remains asserted for four ECLK periods.
Disabling the ECLK signal output does not affect the delay mechanism. Refer to the timing diagrams in
Both pre- and post-address cycles are always present during the address phase of an EBUS cycle. The post-
address cycle is one PCI period long and provides MUSYCC time to transition between the address phase and the
following data phase. The pre- and post-address cycles are not included in the address duration.
3.1.6
MUSYCC can extend the duration that the data bits are valid for any EBUS data phase by specifying a value from
0–7 in ELAPSE bit field (refer to
ECLK periods the data bits remain asserted. That is, a value of 0 specifies the data that remains asserted for one
ECLK period, and a value of 7 specifies the data that remains asserted for eight ECLK periods. Disabling the ECLK
signal output does not affect the delay mechanism. Refer to the timing diagrams in
A pre-data and post-data cycle are always present during the data phase of an EBUS cycle. The pre-data cycle is
one PCI period long and provides MUSYCC setup and hold time for the data signals. The post-data cycle is one
ECLK period long and provides MUSYCC time to transition between the data phase and the following bus cycle
termination. The pre- and post-data cycles are not included in the data duration.
3.1.7
MUSYCC can be configured to wait a specified amount of time after it releases the EBUS and before it requests
the EBUS a subsequent time. This is accomplished by specifying a value 0–7 in BLAPSE bit field (refer to
6, Global Configuration
immediately after releasing the bus; that is, a value of 0 specifies MUSYCC will wait for one ECLK period, and a
value of 5 specifies six ECLK periods. Disabling the ECLK signal output does not affect this wait mechanism. Refer
to the timing diagrams in
The bus grant signal (HLDA/BG*) is deasserted by the bus arbiter only after the bus request signal (HOLD/BR*) is
deasserted by MUSYCC. As the amount of time between bus request deassertion and bus grant deassertion can
vary from system to system, it is possible for a misinterpretation of the “old” bus grant signal as an approval to
access the EBUS. MUSYCC provides the flexibility through the bus access interval feature to wait a specific
number of ECLK periods between subsequent bus requests. (Refer to EBUS arbitration timing diagrams,
13, EBUS Write/Read Transactions, Intel-Style
Style.)
28478-DSH-002-E
7.2.4
for more details.
Interrupt
Address Duration
Data Duration
Bus Access Interval
Section 7.2.4
Descriptor). The value specifies the additional ECLK periods MUSYCC waits
3Ch). Also, the Interrupt Line bit field in the same register is set up by the system
Preliminary Information / Mindspeed Proprietary and Confidential
Table 5-6, Global Configuration
Mindspeed Technologies
Table 5-6, Global Configuration
for more details.
and
Figure 7-14, EBUS Write/Read Transactions, Motorola-
Descriptor). The value specifies the additional
®
Descriptor). The value specifies the
Section 7.2.4
Expansion Bus (EBUS)
Table 2-
for more details.
Section
Figure 7-
Table 5-
50