28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 76

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

4.5.4
A Change of Frame Alignment (COFA) condition is defined as a frame synchronization event detected when it is
not expected, and includes the detection of the first occurrence of frame synchronization when none is present.
When the serial interface detects a COFA condition, an internal COFA signal is asserted for one frame period.
During that period, MUSYCC’s channel group processor terminates all active messages during the channel map
processing.
For each receiver channel found to be active and processing a message during the RCOFA event, each of these
channels’ Buffer Status Descriptor is written with the COFA error encoding. The Buffer Status Descriptor is written
if configured to do so in the Group Configuration Descriptor. MUSYCC then proceeds to the next Message
Descriptor in the list of messages.
When the internal COFA is deasserted, MUSYCC generates an Interrupt Descriptor with the COFA error encoding
if the interrupt is not masked in the Group Configuration Descriptor. If a synchronization signal is received (low-
to-high transition on TSYNC or RSYNC) while the internal COFA is asserted, an Interrupt Descriptor with the
COFA interrupt encoding is generated immediately if this interrupt is not masked. COFA detection is not applicable
to the N x 64 serial port mode.
4.5.5
The Receiver Out-of-Frame (ROOF) signal is asserted by the physical T1 or E1 interface sourcing the channelized
data to MUSYCC. This signal indicates the interface device has lost frame synchronization.
In the case of multiplexed E1 lines (2xE1 or 4xE1), the ROOF input signal on a given port can be asserted and
deasserted as time slots are received from an out-of-frame E1 followed by an in-frame E1.
The state of ROOF is evaluated on a bit-by-bit basis when processing data from a time slot. When ROOF assertion
is detected by the receiver serial interface, MUSYCC checks the OOFABT bit in the Group Configuration
Descriptor. If the OOFABT bit is set (i.e., 1), MUSYCC terminates any active messages for all mapped and active
channels in the channel group. If the OOFABT bit is not set (i.e., 0), MUSYCC continues to process the received
data but still asserts the OOF Interrupt Descriptor unless it is masked.
For each receive message terminated during the OOF condition, the corresponding Message Descriptor’s owner
bit is returned to the host, and a Buffer Status Descriptor is written with the OOF error encoding. The Buffer Status
Descriptor is written to host memory only if configured to do so on a per group basis in the Group Configuration
Descriptor.
MUSYCC then proceeds to the next Message Descriptor in the list of messages. Two frame synchronization
events (via external sync or flywheel sync) after ROOF is asserted, MUSYCC generates an interrupt descriptor
with the OOF error encoding if the interrupt is not masked in the Group Configuration Descriptor.
As ROOF is deasserted, MUSYCC immediately restarts normal bit level processing on all mapped and active
channels. Two frame synchronization events after deassertion of ROOF is detected, MUSYCC generates an
interrupt descriptor with the Frame Recovery (FREC) interrupt encoding if the interrupt is not masked (as indicated
in
28478-DSH-002-E
Table 5-10, Group Configuration
Change-of-Frame Alignment
Out-of-Frame
Preliminary Information / Mindspeed Proprietary and Confidential
Descriptor).
Mindspeed Technologies
®
Serial Interface
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