28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 64

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

3.1.8
Using the EBUS to perform extensive polling of peripheral devices substantially increases PCI bus utilization. The
EBUS interface within MUSYCC performs single dword access without burst cycles. Also, the access time for data
on the EBUS is dependent on how fast the peripherals respond to an EBUS read or write cycle.
PCI write access cycles targeted at the EBUS are not at issue because they complete immediately. MUSYCC’s
host interface autonomously completes writing data to the EBUS after successfully terminating the host’s PCI write
access cycle.
PCI read access cycles targeted at the EBUS are at issue because they cause MUSYCC’s host interface to first
claim the access cycle, then immediately initiate a PCI Target Retry sequence. This causes the PCI bridge device
to retry the same EBUS access at a later time. Concurrently, the EBUS interface is activated to access the
requested data from the EBUS. Because this process may take many EBUS clock cycles to complete, the host
interface is capable of holding off each retry request by initiating a subsequent Target Retry sequence until the
EBUS interface delivers the required data to the host interface. Target Retry sequences may occur multiple times.
As EBUS data is made available to the host interface, and on the next retry from the bridge chip, the host interface
checks whether or not the retry cycle address matches the address latched in during the initial EBUS access cycle
and, if so, forwards the EBUS data to the requester. If the addresses do not match, MUSYCC starts a new EBUS
access cycle.
The amount of time to complete a single EBUS cycle accessing a single dword at a time and the number of bus
turnovers between successive retries affect PCI bus utilization. To avoid affecting the PCI bus adversely, systems
must be designed to throttle EBUS access or use a local microprocessor on the EBUS to filter the information from
peripheral devices.
3.1.9
The MPUSEL bit field specifies the type of microprocessor interface to use for the EBUS. (See
Configuration
Table 3-1
Table 3-1.
Table 3-2
28478-DSH-002-E
FOOTNOTE:
Signal
HOLD
HLDA
ALE*
WR*
RD*
describes the effective signals when Intel-style protocol is selected.
shows the effective signals when Motorola-style protocol is selected.
An active low signal is denoted by a trailing asterisk (*).
Intel Protocol Signals
Descriptor.)
Address Latch Enable
Read
Write
Hold Request
Hold Acknowledge
PCI to EBUS Interaction
Microprocessor Interface
Description
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Mindspeed Technologies
Asserted low by MUSYCC to indicate that the address lines contain a valid address.
This signal remains asserted for the duration of the access cycle.
Strobed low by MUSYCC to enable data reads out of the device. Held high during
writes.
Strobed low by MUSYCC to enable data writes into the device. Held high during reads.
Asserted high by MUSYCC when it requests the EBUS from a bus arbiter.
Asserted high by bus arbiter in response to HOLD signal assertion. Remains asserted
until after the HOLD signal is deasserted. If the EBUS is connected and there are no
bus arbiters on the EBUS, this signal must be asserted high at all times.
®
Interpretation
Expansion Bus (EBUS)
Table 5-6, Global
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