28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 3

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

CN8478/74A/72A/71A
Multichannel Synchronous
Communications Controller (MUSYCC™)
Product Description
The CN8478, CN8474A, CN8472A, and CN8471A are advanced Multichannel
Synchronous Communication Controllers (MUSYCCs) that format and deformat
up to 256 (CN8478), 128 (CN8474A), 64 (CN8472A), or 32 (CN8471A) HDLC
channels in a single CMOS integrated circuit. MUSYCC operates at Layer 2 of
the Open Systems Interconnection (OSI) protocol reference model. MUSYCC
provides a comprehensive, high-density solution for processing HDLC channels
for internetworking applications such as Frame Relay, ISDN D-channel signaling,
X.25, Signaling System 7 (SS7), DXI, ISUP, and LAN/WAN data transport. Under
minimal host supervision, MUSYCC manages a linked list of channel data
buffers in host memory by performing Direct Memory Access (DMA) of the
HDLC channels.
MUSYCC interfaces with eight independent serial data streams, such as T1/E1
signals, and then transfers data across the popular 32-bit Peripheral Component
Interface (PCI) bus to system memory at a rate of up to 66 MHz. Each serial
interface can be operated at up to 8.192 MHz. Logical channels can be mapped
as any combination of DS0 time slots to support ISDN hyperchannels (Nx64
kbps) or as any number of bits in a DS0 for subchanneling applications (Nx8
kbps). MUSYCC also includes a 32-bit expansion port for bridging the PCI bus to
local microprocessors or peripherals. A JTAG port enables boundary-scan
testing to replace bed-of-nails board testing.
Device drivers for Linux, VxWorks
fee license agreement from Mindspeed. The device drivers include C source
code and supporting software documents.
Functional Block Diagram
28478-DSH-002-E
Configuration
Configuration
Configuration
(Function 0)
(Function 1)
Registers
Interface
Interface
Device
Space
Space
Host
PCI
PCI
PCI
Note: Number of serial interfaces is device-dependent.
Tx/Rx-DMAC
Controller
Preliminary Information / Mindspeed Proprietary and Confidential
DMA
Channel Group 0 – Serial Interface
Channel Group 1 – Serial Interface
Channel Group 2 – Serial Interface
Channel Group 3 – Serial Interface
Channel Group 4 – Serial Interface
Channel Group 5 – Serial Interface
Channel Group 6 – Serial Interface
Channel Group 7 – Serial Interface
®
Boundary Scan and Test Access
operating systems are available under a no-
Expanion Bus Interface
Controller
Interrupt
Mindspeed Technologies
Tx/Rx-BLP
Processor
Bit-Level
Interface
Tx/Rx
Port
®
Distinguishing Features
Applications
256-, 128-, 64-, or 32-channel HDLC
controller
OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
8, 4, 2, or 1 independent serial interfaces
which support
Configurable logical channels
Per-channel protocol mode selection
Per-channel DMA buffer management
Per-channel message length check
Direct PCI bus interface
Local Expansion Bus interface (EBUS)
Low power, 3.3/2.5 V CMOS operation
JTAG boundary scan access port
208-pin PQFP/surface-mount package
BGA
Available in Green (ROHS compliant) as
well as standard version
ISDN basic-rate or primary-rate interfaces
ISDN D-channel controller
Routers
Cellular base station switch controller
CSU/DSU
Protocol converter
Packet data switch
Frame relay switches/Frame Relay Access
Devices (FRAD)
DXI network interface
Distributed packet-based communications
system
Access multiplexer/concentrator
X.25 (LAPB)
Frame relay (LAPF/ANSI T1.618)
ISDN D-channel (LAPD/Q.921)
SS7 support
T1/E1 data streams
DC to 8.192 Mbps TDM busses
Standard DS0 (56, 64 kbps)
Hyperchannel (Nx64)
Subchannel (Nx8)
16-bit FCS mode
32-bit FCS mode
SS7 mode (16-bit FCS)
Transparent mode (unformatted data)
Linked list data structures
Variable size transmit/receive FIFO
Select no length checking
Select from two 12-bit registers to
compare message length
Maximum length 16,384 Bytes
32-bit, 66 or 33 MHz operation
Bus master and slave operation
PCI Version 2.1
32-bit multiplexed address/data bus
Burst access up to 64 Bytes
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