28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 164

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

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Effects:
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Channel Level Recovery Actions:
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6.4.9.4.2
In the case of overflow due to internal FIFO buffer overrun, the internal FIFO buffer is not completely copied to
shared memory before more received data bits must be stored in the FIFO buffer. MUSYCC has access to a
shared memory buffer in this case.
Reasons:
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Effects:
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Channel Level Recovery Actions:
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6.4.9.4.3
In the case of a Change of Frame Alignment while receiving an HDLC message (T1/E1 modes
signal transitions from low to high unexpectedly by the “frame synchronization flywheel mechanism.” This error
applies only to ports configured for T1, E1, 2xE1, or 4xE1 signals. Frame synchronization indicates the location of
time slot 0 in the serial data stream. Lacking frame synchronization, the received channelized data becomes
unaligned and unmappable. This error affects all active channels in the channel group.
Reason:
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Effects:
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28478-DSH-002-E
Congestion of the PCI bus.
The Interrupt Descriptor in Interrupt Queue with ERROR = ONR, DIR = 0.
The received data in the internal FIFO buffer is discarded and lost to the host.
The channel is deactivated.
Reactivate the channel.
Degradation of the host subsystem or application software performance.
Congestion of the PCI bus.
MUSYCC writes the Interrupt Descriptor in Interrupt Queue with ERROR = BUFF, DIR = 0.
The received data in the internal FIFO is discarded and lost to the host.
No additional activity on the PCI bus for this channel direction.
Receive channel activity is suspended.
If possible, increase internal FIFO buffer space for this channel.
Alleviate loading of the PCI bus.
Reactivate receive channel with a channel activate or channel jump service request or with a slave write into
the Receive Channel Configuration Table.
A signal failure detected by the physical interface providing the serial data, clock frequency, and
synchronization to the serial interface on MUSYCC.
MUSYCC writes the Interrupt Descriptor in Interrupt Queue with ERROR = COFA, DIR = 0.
If OOFABT bit field is set to 0 in the Group Configuration Descriptor, then continue channel activity. That is,
received data bits are sampled and eventually copied into shared memory.
Overflow Due to Internal FIFO Buffer Overrun (BUFF)
Change of Frame Alignment (T1/E1 Modes) (COFA)
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
)
Basic Operation
, the RSYNC input
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