28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 167

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

When in Octet counting mode, a 4-bit bad octet counter is incremented for every received octet until a condition is
met to exit this mode. As the counter rolls over from 15 to 0, the SUERM counter is incremented by one. This mode
is exited when a correctly checked signal unit (unerrored message) is detected.
Each time the octet counting mode is entered, the value of 4-bit bad octet counter is reset.
6.5.6
The SUERM counter is decremented when 256 unerrored messages are received. An unerrored message
indicates that a short frame or long frame error was not detected, no octet alignment error was detected, and no
CRC error was detected. Each unerrored message increments an 8-bit good message counter. When this counter
rolls over from 255 to 0, the SUERM counter is decremented by one.
While in octet counting mode, the value of the 8-bit good message counter is maintained from the last non-octet
counting mode and starts to increment again from that value when a good message causes an exit from the octet
counting mode.
When the SUERM counter decrements, the maskable interrupt SDEC is generated to the host indicating this
condition.
6.6
The transmit and receive Buffer Descriptors and Buffer Status Descriptors are designed to facilitate a mechanism
known as “self-servicing buffers.” This mechanism allows the host to configure MUSYCC to fill a linked list of data
buffers as it receives a complete message through a receive channel, and empty that same list of data buffers
through a transmit channel without any further host intervention.
The mechanism works as follows:
1. Host initializes linked list of Message Descriptors in shared memory.
2. Host configures receive channel to point to first Message Descriptor.
3. Host configures transmit channel to point to the same Message Descriptor.
4. The OWNER bit field in the Buffer Descriptor in the Message Descriptor is set to 0. Therefore, for the
5. Both receive and transmit channel are activated.
6. As the receiver detects a valid incoming message, it begins filling the first data buffer from the linked list. The
7. As the receiver fills the first buffer, it writes the Receive Buffer Status Descriptor (and sets OWNER to 1) and
8. The transmit channel detects the OWNER set to 1 for the first Transmit Data Buffer, assumes ownership of the
9. Upon detecting the end of a message, the receiver writes the Receive Buffer Status Descriptor and marks this
10. When the transmitter detects the End of Message marking in the last buffer, the transmitter sends the final
11. Go to step 6 to continue processing the next message.
28478-DSH-002-E
transmitter, the buffer is owned by the host; for the receiver, the buffer is owned by MUSYCC.
transmitter remains idle, polling the OWNER bit in the Transmit Buffer Descriptor.
moves to the Next Message Pointer which identifies the next Receive Data Buffer on the linked list.
buffer, and begins emptying data to the serial port.
last buffer as containing the End of Message and sets the buffer length field, BLEN to indicate the amount of
data received in this last buffer.
BLEN amount of data out the serial port and writes the Transmit Buffer Status Descriptor (and sets OWNER
to 0) and moves into the idle state again.
SUERM Counter Decrementing
Self-Servicing Buffers
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Basic Operation
154