28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 104

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

mapping is decoded. The host can instruct MUSYCC to read in the maps from shared memory by issuing the
appropriate service request; otherwise, the host must perform multiple direct writes into MUSYCC’s internal
registers by appropriately addressing PCI access cycles for MUSYCC.
Accessing the Time Slot Map or Subchannel Map within MUSYCC requires that a serial line clock be present at the
serial interface. If a clock is not present, writes are ignored, and reads return all 1s.
The host can read and write the Receive Time Slot Map from within MUSYCC; however the host can only write the
Transmit Time Slot Map into MUSYCC. The transmit maps are stored in write-only registers. Reading transmit
maps results in all 1s being returned.
The host can read and write the Receive Subchannel Map from within MUSYCC; however, the host can only write
the Transmit Subchannel Map into MUSYCC. The transmit maps are stored in write-only registers. Reading the
transmit map results in all 1s being returned.
5.2.3
The channel level descriptors contain information necessary to configure channel registers.
5.2.3.1
The Channel Configuration Descriptor configures aspects of the channel common to all messages passing through
the channel. One descriptor exists for each logical channel direction.
Table 5-18
Table 5-18.
28478-DSH-002-E
Field
29:24
21:16
14:12
Bit
31
30
23
22
15
PADJ
RSVD
BUFFLOC[5:0]
INV
RSVD
BUFFLEN[5:0]
EOPI
PROTOCOL[2:0]
lists the values and description of each channel configuration descriptor.
Channel Configuration Descriptor (1 of 3)
Name
Channel Level Descriptors
Channel Configuration Descriptor
Preliminary Information / Mindspeed Proprietary and Confidential
00h–3Fh
00h–3Fh
Value
4–7
0
1
0
0
0
0
1
0
1
2
3
Mindspeed Technologies
Pad Count Adjustment disabled. No adjustment is made to the value of PADCNT if Zero
Insertions is detected.
Pad Count Adjustment enabled. The value of PADCNT is reduced if Zero Insertions is
detected. This adjustment is required for rate adaptive applications such as ITU-T
Recommendation V.120.
Reserved
Channel Buffer Location Index. Starting location of internal FIFO data buffer for this channel
and direction.
Data Inversion disabled. All data bits in message are not inverted between shared memory
and MUSYCC.
Reserved.
Internal Data Buffer Length. Number of internal FIFO data buffer locations allocated to this
channel and direction equals 2 x (BUFFLEN+1) dwords.
End Of Padfill Interrupt disabled. Transmit Only. After outputting last padfill code, do not
generate interrupt indicating condition.
End of Padfill Interrupt enabled.
TRANSPARENT
SS7-HDLC-FCS16
HDLC-FCS16
HDLC-FCS32
Reserved.
®
Description
Memory Organization
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