28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 121

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 5-32.
5.2.6
5.2.6.1
Interrupt management resources are automatically reset upon the following:
•
•
•
•
•
•
MUSYCC uses two interrupt queues: one is internal to MUSYCC and is controlled exclusively by the interrupt
controller logic; the other is the Interrupt Queue in shared memory, which is allocated and administered by the host,
but written to by MUSYCC.
Upon initialization, the data in the status descriptor is reset to 0s, indicating the first location for next descriptor, the
queue is not full, and no descriptors are in the queue. Any existing descriptors in the internal queue are discarded.
The Interrupt Status Descriptor stores the location of the next descriptor to be read by the host, a queue full
indicator, and a count of interrupts last written into shared memory since the last read of the Interrupt Status
Descriptor.
The host must allocate sufficient shared memory space for the Interrupt Queue. Up to 32,768 dwords of queue
space are accessible by MUSYCC, setting the upper limit for the queue size. MUSYCC requires a minimum of two
dwords of queue space, setting the lower limit for the queue size.
The host must store the pointer to the queue and the queue’s length in dwords in MUSYCC within the Interrupt
Queue Descriptor register. This is done by issuing the appropriate service request to MUSYCC. As MUSYCC takes
in the new values, it automatically resets the controller logic as indicated above. This mechanism can also be used
to switch interrupt queues while MUSYCC is in full operation.
5.2.6.2
Interrupt conditions are detected in both error and non-error cases. MUSYCC makes a determination based on
channel group, channel, and device configuration, whether reporting the condition is to be masked or whether an
Interrupt Descriptor is to be sent to the host. If the interrupt is not masked, MUSYCC generates a descriptor and
stores it internally prior to transfer to the Interrupt Queue in shared memory.
28478-DSH-002-E
FOOTNOTE:
(1)
Field
14:0
Bit
15
The INTFULL status is read—cleared bit field.
Hardware reset
Soft-chip reset service request
Global initialization service request
Read Interrupt Queue Descriptor service request
Direct memory write to Interrupt Queue Pointer
Direct memory write to Interrupt Queue Length
INTCNT[14:0]
INTFULL
Interrupt Status Descriptor
Name
Interrupt Handling
Initialization
Interrupt Descriptor Generation
Preliminary Information / Mindspeed Proprietary and Confidential
Value
—
0
1
Interrupt Queue Not Full—shared memory.
Interrupt Queue Full—shared memory.
Interrupt Count. 15-bit value indicates the number of interrupts pushed into the Interrupt Queue since
the last reading of the Interrupt Status Descriptor. All writes to this bit field register are ignored.
Mindspeed Technologies
(1)
®
(1)
Description
Memory Organization
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