28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 150

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

DMACs access the data to transmit or store the received data to shared memory (via the host interface). Each
DMAC seeks out the next Message Descriptor to service for each active channel and direction. This information is
available from the Channel Group Descriptor in shared memory which has information locating the message list for
each channel direction. A Buffer Descriptor within each Message Descriptor along with the protocol mode set for
the channel-direction drives the treatment of the receive and transmit bit stream.
Bit-level operations vary between HDLC and transparent modes. The differences relate to protocol-specific
support, as well as to the treatment of the bit stream during abnormal conditions. Additionally, bit-level operations
are independent and sometimes differ between the transmitter and the receiver.
The following items apply to all event and error handling as described in the transmit and receive sections which
follow:
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6.4.7.1
The transmitter initiates data transfer from shared memory to the serial interface only if the following conditions are
true:
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If the TXENBL bit is set to 0, the output signal is a three-state signal. If the channel is not mapped or is inactive, the
transmitter either outputs a three-state or an all 1s signal depending on the state of the bit field TRITX in the Group
Configuration Descriptor.
6.4.7.2
The receiver transfers data from the serial interface to memory buffers in shared memory only if all the following
conditions are true:
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If any one of the above conditions is not true, the receiver ignores the incoming data stream.
Data transfer consists of MUSYCC first seeking out the next Message Descriptor from the Channel Group
Descriptor in shared memory for each active channel. The Buffer Descriptor in each Message Descriptor plus the
protocol mode set for the channel dictates the treatment of the incoming bit stream.
28478-DSH-002-E
During bit level operations, events and errors can affect the outcome message processing. Unless masked, all
events and errors generate Interrupt Descriptors within MUSYCC. Interrupt Descriptors identify the error or
event condition, the transmit or receive direction, and the channel and channel group number affected.
If a channel is suspended, enters an idle mode, enters an abort mode, or is autonomously turned off by
MUSYCC during bit-level operations, a channel reactivation must occur by either a Channel Activation Service
Request or a Channel Jump Service Request. This is referred to as “requiring reactivation.”
The bit fields INHTBSD and INHRBSD in the Group Configuration Descriptor specify whether or not MUSYCC
can write a Buffer Status Descriptor into a Message Descriptor to indicate that MUSYCC has completed
servicing the descriptor.
In cases where bit-level operations continue normally, the DMAC accesses the Next Message Pointer from the
current Message Descriptor. This accesses the next Message Descriptor in the chain of descriptors for a
particular channel and direction. Each Message Descriptor indicates whether or not the host or MUSYCC
owns the descriptor.
TXENBL bit is set to 1 in the Group Configuration Descriptor.
Transmit channel is mapped to logical channel(s) in Transmit Time Slot Map.
Transmit channel is (re)activated (via service request).
RXENBL bit is set to 1 in the Group Configuration Descriptor.
Receive channel is mapped to one or more logical channel(s) in Receive Time Slot Map.
Receive channel is (re)activated (via service request).
Transmit
Receive
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