28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 38

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 1-4.
28478-DSH-002-E
48-51, 54,
56-58, 61,
65-66, 69-
72, 88, 90-
94, 97, 99,
101-103,
105-109
43
45
59, 74, 87,
100
86
75
76
79
83
Pin No.
MQFP
CN8478 Hardware Signal Definitions (4 of 6)
PCLK
PAR
IRDY*
TRDY*
AD[31:0]
PRST*
CBE[3:0]*
FRAME*
STOP*
Pin Label
Preliminary Information / Mindspeed Proprietary and Confidential
PCI Address
and Data
PCI Clock
PCI Reset
PCI Command
and Byte Enables
PCI Parity
PCI Frame
PCI Initiator Ready
PCI Target Ready
PCI Stop
Signal Name
Mindspeed Technologies
s/t/s I/O
s/t/s I/O
s/t/s I/O
s/t/s I/O
t/s I/O
t/s I/O
t/s I/O
I/O
I
I
AD[31:0] is a multiplexed address/data bus. A PCI transaction consists of
an address phase during the first clock period followed by one or more
data phases. AD[7:0] is the LSB.
PCLK provides timing for all PCI transitions. All PCI signals except PRST*,
INTA*, and INTB* are synchronous to PCLK and are sampled on the rising
edge of PCLK. MUSYCC supports a PCI clock up to 66 MHz.
This input resets all functions on MUSYCC.
During the address phase, CBE[3:0]* contain command information;
during the data phases, these pins contain information denoting which
byte lanes are valid.
PCI commands are defined as follows:
The number of 1s on PAR, AD[31:0], and CBE[3:0]* is an even number.
PAR always lags AD[31:0] and CBE* by one clock. During address phases,
PAR is stable and valid one clock after the address; during the data phases
it is stable and valid one clock after TRDY* on reads and one clock after
IRDY* on writes. It remains valid until one clock after the completion of
the data phase.
FRAME* is driven by the current master to indicate the beginning and
duration of a bus cycle. Data cycles continue as FRAME* stays asserted.
The final data cycle is indicated by the deassertion of FRAME*. For a non-
burst, one-data-cycle bus cycle, this pin is only asserted for the address
phase.
IRDY* asserted indicates the current master’s readiness to complete the
current data phase.
TRDY* asserted indicates the target’s readiness to complete the current
data phase.
STOP* asserted indicates the selected target is requesting the master to
stop the current transaction.
Oh
Ah
Bh
Ch
Dh
1h
6h
7h
Eh
Fh
CBE[3:0]
®
0000b
1010b
1011b
1100b
1101b
0001b
0110b
0111b
1110b
1111b
Definition
Memory Write and Invalidate
Interrupt Acknowledge
Memory Read Multiple
Configuration Write
Configuration Read
Dual Address Cycle
Memory Read Line
Command Type
Memory Write
Memory Read
Special Cycle
25