PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 110

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Interrupts
•
Figure 8-7
Task Status saved on the System Stack
The interrupt request flag of the source that is being serviced is cleared. The IP is loaded
with the vector associated with the requesting source (the CSP is cleared in case of
segmentation) and the first instruction of the service routine is fetched from the
respective vector location, which is expected to branch to the service routine itself. The
data page pointers and the context pointer are not affected.
When the interrupt service routine is left (RETI is executed), the status information is
popped from the system stack in the reverse order, taking into account the value of bit
SGTDIS.
Context Switching
An interrupt service routine usually saves all the registers it uses on the stack, and
restores them before returning. The more registers a routine uses, the more time is
wasted with saving and restoring. The INCA-D allows to switch the complete bank of
CPU registers (GPRs) with a single instruction, so the service routine executes within its
own, separate context.
The instruction “SCXT CP, #New_Bank” pushes the content of the context pointer (CP)
on the system stack and loads CP with the immediate value “New_Bank”, which selects
a new register bank. The service routine may now use its “own registers”. This register
bank is preserved, when the service routine terminates, ie. its contents are available on
the next call.
Before returning (RETI) the previous CP is simply POPped from the system stack, which
returns the registers to the original bank.
Note: The first instruction following the SCXT instruction must not use a GPR.
Data Sheet
110
2003-03-31