PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 594

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
– Short Hardware Reset
24.1.1
This reset type is generated and controlled in the core. The core provides a control signal
(8TCL) to start the reset sequence and to indicate this reset type in the WDTCON
register. As long as the reset sequence is running the internal system reset signal RST
is generated. The trailing edge of RST starts program execution.
After SW reset the startup configuration is latched in again.
24.1.2
When the watchdog timer is not disabled during the initialization or serviced regularly
during program execution it will overflow and trigger the watchdog timer reset (signal to
the core). Other than a hardware reset the watchdog timer reset completes a running
external bus cycle. Then the core provides a control signal (WDT Reset Active, 8TCL) to
the SCU to start the reset sequence. As long as the reset sequence is running the
internal system reset signal RST is generated. The trailing edge of RST starts program
execution.
Note: The watchdog timer reset cannot occur while the device is in bootstrap loader
24.2
A minimum reset duration of 2048 TCL (1024 CPU clock cycles) is necessary for latching
of the startup/reset configuration from P0. This minimum reset time is controlled with
execution of the so called reset sequence.
The reset sequence is started with every reset type. As long as the reset sequence is
running, short reset types (SHWR, WDTR and SWR) are lengthened to the minimum
reset duration
24.3
In case of a hardware reset the internal system reset time as controlled with the external
reset input RSTIN (power-on or long HW-reset) or with the reset sequence time (short
Note: The hardware reset is also used for wakeup from power down state; in this case
the internal system reset will be lengthened (execution of 1. instruction delayed) until
the oscillator and PLL have been stabilized.
The active RSTIN time of a short hardware reset is between 16 TCL and 2048 TCL.
If the RSTIN signal is active for at least 16 TCL clock cycles, the internal reset
sequence is started (see below). If the RSTIN signal is active for more then 2048 TCL,
its a long hardware reset.
The short hardware reset type is also indicated to the WDT block.
mode!
Software Reset
WDT Reset
Reset Sequence Control
Reset Lengthening Control (Start Delay)
594
System Reset
PSB 21473
2003-03-31
INCA-D