PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 131

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

9.1.1
For external memory access PORT0 is used as data bus or address/data bus.
Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O
(provided that no other bus mode is enabled).
PORT0 is also used to select the system startup configuration. During reset, PORT0 is
configured to input, and each line is held high through an internal pullup device. Each
line can now be individually pulled to a low level (see DC-level specifications in the
respective Data Sheets) through an external pulldown device. A default configuration is
selected when the respective PORT0 lines are at a high level. Through pulling individual
lines to a low level, this default can be changed according to the needs of the
applications.
The internal pullup devices are designed such that an external pulldown resistors (see
specification) can be used to apply a correct low level. These external pulldown resistors
can remain connected to the PORT0 pins also during normal operation, however, care
has to be taken such that they do not disturb the normal function of PORT0 (this might
be the case, for example, if the external resistor is too strong).
With the end of reset, the selected bus configuration will be written to the BUSCON0
register. The configuration of the high byte of PORT0, will be copied into the special
register RP0H. This read-only register holds the selection for the number of chip selects
and segment addresses. Software can read this register in order to react according to
the selected configuration, if required.
Note: When the reset is terminated, the internal pullup devices must be switched off by
During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intra-
segment address as an alternate output function. PORT0 is then switched to high-
impedance input mode to read the incoming instruction or data. In 8-bit data bus mode,
two memory cycles are required for word accesses, the first for the low byte and the
second for the high byte of the word. During write cycles PORT0 outputs the data byte
or word after outputting the address.
During external accesses in demultiplexed bus modes PORT0 reads the incoming
instruction or data word or outputs the data byte or word.
Data Sheet
Software using bit BCLR of register P0(L/H)PUDEN.x, and PORT0 will be
switched to the appropriate operating mode.
Alternate Functions of PORT0
131
Parallel Ports
PSB 21473
2003-03-31
INCA-D