PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 586

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Power Reduction Modes
SFRs and ports to their default state, but will not change the contents of the internal
RAM.
There are two levels of protection against unintentionally entering Power Down mode.
First, the PWRDN (Power Down) instruction which is used to enter this mode has been
implemented as a protected 32-bit instruction. Second, this instruction is effective only
if the NMI (Non Maskable Interrupt) pin is externally pulled low while the PWRDN
instruction is executed. The microcontroller will enter Power Down mode after the
PWRDN instruction has completed.
This feature can be used in conjunction with an external power failure signal which pulls
the NMI pin low when a power failure is imminent. The microcontroller will enter the NMI
trap routine which can save the internal state into RAM. After the internal state has been
saved, the trap routine may set a flag or write a certain bit pattern into specific RAM
locations, and then execute the PWRDN instruction. If the NMI pin is still low at this time,
Power Down mode will be entered, otherwise program execution continues. During
power down the voltage at the V
pins can be lowered to 2.5 V while the contents of the
DD
internal RAM will still be preserved.
The initialization routine (executed upon reset) can check the identification flag or bit
pattern within RAM to determine whether the controller was initially switched on, or
whether it was properly restarted from Power Down mode.
23.4
Status of Output Pins during Idle and Power Down Mode
During Idle mode the CPU clocks are turned off, while all peripherals continue their
operation in the normal way. Therefore all ports pins, which are configured as general
purpose output pins, output the last data value which was written to their port output
latches. If the alternate output function of a port pin is used by a peripheral, the state of
the pin is determined by the operation of the peripheral.
Port pins which are used for bus control functions go into that state which represents the
inactive state of the respective function (eg. WR), or to a defined state which is based on
the last bus access (eg. BHE). Port pins which are used as external address/data bus
hold the address/data which was output during the last external memory access before
entry into Idle mode under the following conditions:
P0H outputs the high byte of the last address if a multiplexed bus mode with 8-bit data
bus is used, otherwise P0H is floating. P0L is always floating in Idle mode.
PORT1 outputs the lower 16 bits of the last address if a demultiplexed bus mode is used,
otherwise the output pins of PORT1 represent the port latch data.
Port 4 outputs the segment address for the last access on those pins that were selected
during reset, otherwise the output pins of Port 4 represent the port latch data.
During Power Down and Sleep Mode the oscillator and the clocks to the CPU and to
the peripherals are turned off. Like in Idle mode, all port pins which are configured as
Data Sheet
586
2003-03-31