PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 27
PSB21473FV13XT
Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21473FV13XT.pdf
(664 pages)
Specifications of PSB21473FV13XT
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
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Table 2-5
Pin No. Symbol
117
116
26
Table 2-6
Pin No. Symbol
105
104
103
108
107
106
Data Sheet
RSTIN
RSTOUT O
NMI
TEST
TCK
TDI
TDO
TMS
TRST
RESET
Boundary Scan, JTAG , OCDS
Input (I)
Output (O)
Open Drain
(OD)
I
I
Input (I)
Output (O)
Open Drain
(OD)
I
I
I
O
I
I
Function
Reset Input. A low level at this pin for a specified
duration while the oscillator is running, resets the
device.
(Internal pull-up provided).
Internal Reset Indication Output. This pin is set to a
low level when the device is executing either a
hardware-, software- or a watchdog timer reset.
RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low
transition at this pin causes the CPU to vector to the
NMI trap routine. When the PWRDN (power down)
instruction is executed, the NMI pin must be low in
order to force the CPU to go into power down
mode. If NMI is high, when PWRDN is executed,
the device will continue to run in normal mode. If
not used, pin NMI should be pulled high externally.
However, it is possible to tie NMI permanently to
VSS.
Function
Internal Test Mode Enable
(tied to VSS)
Test Clock Input (internal pull-up)
Test Data Input (internal pull-up)
Boundary Scan Test Data Output
Test Mode Select (internal pull-up)
Test Reset (internal pull-down)
27
Pin Descriptions
PSB 21473
2003-03-31
INCA-D
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