PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 85

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

8.1
The INCA-D provides up to 27 separate interrupt nodes that may be assigned to 16
priority levels. Each source of an interrupt or PEC request is supplied with a separate
interrupt control register and interrupt vector. The control register contains the interrupt
request flag, the interrupt enable bit, and the interrupt priority of the associated source.
The INCA-D provides a vectored interrupt system. In this system specific vector
locations in the memory space are reserved for the reset, trap, and interrupt service
functions. Whenever a request occurs, the CPU branches to the location that is
associated with the respective interrupt source. This allows direct identification of the
source that caused the request. The only exceptions are the class B hardware traps,
which all share the same interrupt vector. The status flags in the Trap Flag Register
(TFR) can then be used to determine which exception caused the trap. For the special
software TRAP instruction, the vector address is specified by the operand field of the
instruction, which is a seven bit trap number.
The reserved vector locations build a jump table in the low end of the INCA-D’s address
space (segment 0). The jump table is made up of the appropriate jump instructions that
transfer control to the interrupt or trap service routines, which may be located anywhere
within the address space.
Each jump table entry occupies 2 words, except for the reset vector and the hardware
trap vectors, which occupy 4 or 8 words.
The table below lists all sources that are capable of requesting interrupt or PEC service
in the INCA-D, the associated interrupt vectors, their locations, their trap numbers and
the SFR addresses of associated interrupt control registers. It also lists the mnemonics
of the corresponding Interrupt Enable flags. The mnemonics are composed of a part that
specifies the respective source, followed by a part that specifies their function
(IE=Interrupt Enable flag). The same composition is used for the mnemonics of
according interrupt request flags (IR=Interrupt Request flag; example: CC0IR belongs to
interrupt source CC0INT) and for the names of according interrupt control registers
(IC=Interrupt Control; example: CC0IC) which are not included in Table 8-1.
Table 8-1
Nr.
irq(0)
irq(1)
irq(2)
irq(3)
Data Sheet
Source of Interrupt
or PEC Service
Request
GPT Timer 2
GPT Timer 3
USB Endpoint 1
USB Device
Interrupts
Interrupt System Structure
INCA-D Interrupts and PEC Service Requests
Interrupt
Name
T2INT
T3INT
USBEP1INT
USBINT
85
Enable
Flag
T2IE
T3IE
USBEP1IE
USBIE
Vector
Location
00’005C
00’0084
00’0080
00’00A4
H
H
H
H
Trap
Number
17
21
20
29
H
H
H
H
PSB 21473
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Interrupts
2003-03-31
INCA-D
D
D
D
D
SFR
Adr.
FF86
FF9E
FF9C
FF9A