PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 48
PSB21473FV13XT
Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21473FV13XT.pdf
(664 pages)
Specifications of PSB21473FV13XT
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
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INCA-D
PSB 21473
Central Processor Unit
6
Central Processor Unit
Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the
arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and
to store the previously calculated results.
Since a four stage pipeline is implemented in the INCA-D, up to four instructions can be
processed in parallel. Most instructions of the INCA-D are executed in one machine
cycle (2 CPU clock cycles) due to this parallelism. This chapter describes how the
pipeline works for sequential and branch instructions in general, and which hardware
provisions have been made to speed the execution of jump instructions in particular. The
general instruction timing is described including standard and exceptional timing.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC), which is automatically invoked by the CPU whenever a code or data
address refers to the external address space. If possible, the CPU continues operating
while an external memory access is in progress. If external data are required but are not
yet available, or if a new external memory access is requested by the CPU, before a
previous access has been completed, the CPU will be held by the EBC until the request
can be satisfied. The EBC is described in a dedicated chapter.
Figure 6-1
CPU Block Diagram
Data Sheet
48
2003-03-31
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