PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 248

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
The Asynchronous / Synchr. Serial Interface
determined by the module clock, the content of S0FDV, the reload value of S0BG and
the operating mode (asynchronous or synchronous).
Register S0BG is the dual-function Baudrate Generator/Reload register. Reading BG
returns the content of the timer BR_VALUE (bits 15...13 return zero), while writing to
S0BG always updates the reload register (bits 15...13 are insiginificant).
An auto-reload of the timer with the content of the reload register is performed each time
S0CON_BG is written to. However, if S0CON_R=’0’ at the time the write operation to BG
is performed, the timer will not be reloaded until the first instruction cycle after
S0CON_R=’1’. For a clean baudrate initialization S0BG should only be written if
S0CON_R=’0’. If S0BG is written with S0CON_R=’1’, an unpredicted behaviour of the
ASC may occur during running transmit or receive operations.
15.1.7.1 Baudrates in Asynchronous Mode
For asynchronous operation, the baudrate generator provides a clock f
with 16 times
BRT
the rate of the established baudrate. Every received bit is sampled at the 7th, 8th and 9th
cycle of this clock. The clock divider circuitry, which generates the input clock for the 13-
bit baudrate timer, is extended by a fractional divider circuitry, which allows the
adjustment of more accurate baudrates and the extension of the baudrate range.
The baudrate of the baudrate generator depends on the following input clock, bits and
register values :
• Input clock f
MOD
• Selection of the baudrate timer input clock f
by bits S0CON_FDE and S0CON_BRS
DIV
• If bit S0CON_FDE=1 (fractional divider) : value of register S0CON_FDV
• value of the 13-bit reload register S0BG
The output clock of the baudrate timer with the reload register is the sample clock in the
asynchronous modes of the ASC. For baudrate calculations, this baudrate clock f
is
BR
derived from the sample clock f
by a division by 16.
DIV
Data Sheet
248
2003-03-31