PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 212

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
General Purpose Timer Unit
x =5 y = 6
Note: Line ’*’ only affected by over/underflows of T6, but NOT by software
modifications of T6OTL.
Figure 14-20 Concatenation of Core Timer T6 and Auxiliary Timer T5
Capture/Reload Register CAPREL in Capture Mode
This 16-bit register can be used as a capture register for the auxiliary timer T5. This
mode is selected by setting bit T5SC = ‘1’ in control register T5CON. Bit CT3 selects the
external input line CAPIN or the input lines of timer T3 as the source for a capture trigger.
Either a positive, a negative, or both a positive and a negative transition at line CAPIN
can be selected to trigger the capture function, or transitions on input T3IN or input
T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bit field CI in
register T5CON.
The maximum input frequency for the capture trigger signal at CAPIN is f
/2 (FM2 =
Timer
’1’). To ensure that a transition of the capture trigger signal is correctly recognized, its
level should be held for at least 2 f
cycles (FM2 = ’1’) before it changes.
Timer
When the timer T3 capture trigger is enabled (CT3 = ’1’) register CAPREL captures the
contents of T5 upon transitions of the selected input(s). These values can be used to
measure T3’s input signals. This is useful e.g. when T3 operates in incremental interface
mode, in order to derive dynamic information (speed acceleration) from the input signals.
When a selected transition at the external input line CAPIN is detected, the contents of
the auxiliary timer T5 are latched into register CAPREL, and interrupt request flag CRIR
is set. With the same event, timer T5 can be cleared to 0000
.
H
Data Sheet
212
2003-03-31