PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 541

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

cleared after the setup stage occurred). The first data packet may immediately be sent
from the Host to the control endpoint according to this configuration of bit EPBSn.DIRn,
while NACK will automatically be returned from the Device to the Host in case of a USB
read access. It also causes the direction bit to be changed (EPBSn.DIRn=1, USB read
access).
The direction of the next transfer can also be predicted under software control (bit
EPBSn.SETRDn) to be a USB read access (EPBSn.DIRn=1). This feature is used, if the
direction of the data stage is known and the data packet to be transferred from the CPU
to the Host is setup before the next USB access occurs.
Therefore, the direction bit must be changed under software control, to be able to
transfer the data packet within the first USB read access. Status bit SOD is set under
hardware control to indicate valid data to be read by the CPU in case of a USB write
access, or data to be written by the CPU in case of a USB read access.
22.8.2.3 Status Stage
The status stage always occurs to report the result of the requested operation. A status
stage initiated by the Host, but not terminated according to the setting EPBS0.ESP0=0,
is indicated by a status interrupt (DIRR.STI). Bit EPBS0.ESP0 has to be set under
software control to enable the acknowledge of the status stage.(Please refer also to
page
22.8.3
Table 22-4 lists the standard requests possible. Only the Set_Descriptor,
Get_Descriptor and Synch_Frame requests require intervention from the CPU (refer
also to
are handled by the UDC core and they are transparent to firmware. Since the device
supports multiple device configurations, interfaces and alternate settings, a separate
register CIAR informs the CPU which configuration, interface and alternate setting is
active. For further information please refer to the USB Specification Version 1.1, Chapter
9.4 .
Table 22-4
Request
Get_Status
Clear_Feature
Data Sheet
562).
page
Standard Device Requests
562). The Set_Configuration and Set_Interface standard device requests
Standard Device Requests
Description
This request returns status for the specified recipient, which can be
a device, interface or endpoint.
This request is used to clear or disable a specific feature. The UDC
supports this command to clear the Endpoint_Stall feature for all
supported logical endpoints and to clear the Device_Remote_
WakeUp feature.
541
USB Module
PSB 21473
2003-03-31
INCA-D