PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 50

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
4th –>WRITE BACK:
In this stage all external operands and the remaining operands within the internal RAM
space are written back.
A particularity of the INCA-D are the so-called injected instructions. These injected
instructions are generated internally by the machine to provide the time needed to
process instructions, which cannot be processed within one machine cycle. They are
automatically injected into the decode stage of the pipeline, and then they pass through
the remaining stages like every standard instruction. Program interrupts are performed
by means of injected instructions, too. Although these internally injected instructions will
not be noticed in reality, they are introduced here to ease the explanation of the pipeline
in the following.
Sequential Instruction Processing
Each single instruction has to pass through each of the four pipeline stages regardless
of whether all possible stage operations are really performed or not. Since passing
through one pipeline stage takes at least one machine cycle, any isolated instruction
takes at least four machine cycles to be completed. Pipelining, however, allows parallel
(ie. simultaneous) processing of up to four instructions. Thus, most of the instructions
seem to be processed during one machine cycle as soon as the pipeline has been filled
once after reset (see figure below).
Instruction pipelining increases the average instruction throughput considered over a
certain period of time. In the following, any execution time specification of an instruction
always refers to the average execution time due to pipelined parallel instruction
processing.
Figure 6-2
WRITEBACK
EXECUTE
DECODE
FETCH
time
Sequential Instruction PipeliningI
1 Machine
Cycle
I
1
I
I
2
1
50
I
I
I
3
2
1
I
I
I
I
4
3
2
1
Central Processor Unit
I
I
I
I
5
4
3
2
PSB 21473
I
I
I
I
6
5
4
3
2003-03-31
INCA-D