PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 537

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

22.6
If there is no traffic on the USB line, ie. a ’Start-of-Frame’ token has not been detected
for more than 3 ms, the USB device interrupt DIRR.SBI (’suspend mode begins’) is set.
The control bit DCR.SUSP is set to indicate the suspend mode. As soon as an USB
specification compatible level has been detected, interrupt DIRR.SEI (’suspend mode
ends’) is set.
Two clocks are connected to the USB block. First, the clock signal, which is connected
to the memory management unit. This clock runs at the same frequency as the CPU.
For power saving purposes, this clock can be switched off by setting
CLK_CONF.USB_DIS to ’1’.
Secondly, the 48 MHz clock signal, which clocks the USB device core itself. This clock
can be disabled by setting bit UCLK in the DCR register. This clock can be switched off,
if the USB module is in suspend mode. The DIRR.SEI (’suspend mode ends’) interrupt
is detected even if the UCLK is still disabled.
22.7
The USB module must be functionally initialized by writing 6 configuration bytes which
contain appropriate device information.
Note: The minimum CPU frequency for proper USB operation is 12 MHz.
A well defined procedure must be executed for the switching on the clock for the USB
module:
The switch-on procedure after a hardware reset assures proper operation of the USB
clock system. When the USB clock system is switched on, a software initialization
procedure must follow.
This procedure must execute the following steps:
Figure 22-20 shows the 6-byte configuration block which must be transmitted by the
CPU to the USB module via the USBVAL0 register for each endpoint.
Data Sheet
– PLL is switched on by setting bit PLLEN in register CLK_CONF
– waiting until PLL being locked (CLK_CONF.LOCK = 1)
– USB_DIS bit of the CLK_CONF register has to be cleared
– UCLK bit of the USB Device Control Register DCR has to be set to ’1’
– Setting bit SWR in register DCR starts the software reset operation for the complete
– When the software reset is finished, bit SWR is cleared by hardware and bit DINIT
– The USB module must be functionally initialized from the CPU by writing six
USB module.
is set to indicate the start of the initialization sequence.
configuration bytes for each endpoint to the USBVALn register. Thereafter, bit
DONE0 in register EPBS0 must be set by software.
USB block activation
Initialization of USB Module
537
USB Module
PSB 21473
2003-03-31
INCA-D