PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 602
PSB21473FV13XT
Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21473FV13XT.pdf
(664 pages)
Specifications of PSB21473FV13XT
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
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Data Sheet
Table 24-2
Code Definitions of Startup Configuration
The low order 6 bits of startup configuration define the system mode of operation. These
bits are only decoded in the core for selection and control of the core related modes of
operation, including the normal start after reset with instruction fetch from address
00’0000. Also the configuration of bus type is sampled and latched only in the core.
The following table showes in detail all supported selections for port P0 startup
configuration. In this table, the note 1 is assigned to core related system modes of
operation, which are controlled in the CB-Core.
transparent and not
(P0L.5:2)
Sample event
1 0 1 1
H.7
SMOD
Pin is sampled
WDTR/SWR
R
EMU
ADP
Pin
Pin is not
sampled
SHWR
PONR
LHWR
X :
- :
H.6
R
H.5
Special Modes System Operation
R
Latching of System Startup Configuration from PORT0
Latched into RP0H
X
X
X
X
H.4
SALSEL
Bootstrap Loader
X
X
X
X
Emulation Mode
Adapt Mode
H.3
X
X
X
X
Modes
Mode
X
X
X
X
H.2
CSSEL
X
X
X
X
H.1
BUSCON0
X
X
X
X
PORT0
WRC
H.0
X
X
X
X
602
X
X
X
-
L.7
BUSTYP
X
X
X
-
L.6
X
X
X
FFs
-
Start from internal boot memory
X
X
X
-
L.5
X X
X X
X X
-
internal test mode
internal test mode
L.4
-
SMOD
Comment
L.3
L.2
System Reset
PSB 21473
ADP
2003-03-31
L.1
INCA-D
EMU
L.0
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