PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 157

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Dedicated Pins
The Reference Voltage VREF can be used for biasing external components. The DC
voltage at VREF is the same as at the analog in-/output pins of the analog front-end (if
enabled).
The Bandgap Reference Voltage BGREF (1.2 V) is used for internal references. The
pin BGREF is necessary to connect a filter capacitor (approx. 22nF), which forms a RC-
filter together with an on-chip resistor of about 300k .
Symmetrical differential Microphone Inputs1,2 and 3 MIN1/MIN2/MIN3 and MIP1/MIP2/
MIP3.
Differential Handset earpiece output for 200
transducers HOPx/HONx
Differential Loudspeaker output for 20
loudspeaker LSP/LSN
The Address Latch Enable signal ALE controls external address latches that provide
a stable address in multiplexed bus modes. ALE is activated for every external bus
cycle independent of the selected bus mode, ie. it is also activated for bus cycles with a
demultiplexed address bus. ALE is not activated for internal accesses, ie. the internal
RAM and the special function registers.
The External Read Strobe RD controls the output drivers of external memory or
peripherals when the INCA-D reads data from these external devices. During reset an
internal pullup ensures an inactive (high) level on the RD output.
The External Write Strobe WR/WRL controls the data transfer from the INCA-D to an
external memory or peripheral device. This pin may either provide an general WR signal
activated for both byte and word write accesses, or specifically control the low byte of an
external 16-bit device (WRL) together with the signal WRH (alternate function of P3.12/
BHE). During reset an internal pullup ensures an inactive (high) level on the WR/WRL
output.
Note: Whether RD and WR/WRL remain idle during X-peripheral accesses depends on
the value of bit VISIBLE of register SYSCON.
The line interface consists of the two lines Lla and Llb.
The IOM2-Interface consists of the four lines DCL, FSC, DD, and DU. DCL is the
1.536MHz bit-clock (double-bit clock). FSC the 8kHz frame synchronization signal. DD
and DU serve as serial data out-/input, they require external pull-up resistors. The double
bit-clock at pin DCL can always be output as single-bit-clock (divided by 2) at pin BCL.
The JTAG and OCDS Interface offers an IEEE1149.1 compliant JTAG interface
consisting of the lines TCK, TDI, TDO, TMS, TRST. The JTAG TAP controller allows to
use the JTAG interface for purposes of on-chip debugging. In this OCDS mode,
additional lines BRKIN and BRKOUT are provided for controlling the behaviour of the
CPU. The pin TEST is part of the JTAG interface and required for production test of the
INCA-D. If unused, all pins of the JTAG/OCDS interface can remain unconnected.
Data Sheet
157
2003-03-31