PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 80

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
using synchronous handshaking (via the READY signal). The assertion of the READY
signal by the IOM2 is based on the values programmed in the IOM2 Wait States Register
(IWSR). Without wait states a single c166 access takes 2 XCLK cycles. Hence with a
wait state of 2, the access will last 4 XCLK cycles.
Thus the waitstates for the IOM-2 handler block are not controlled by the XBCON2
register, but by the dedicated IOM-waitstate register IWSR. Please refer to
Chapter 17.6.6.7 for further information.
Wait state for accesses to the USB block
Because the memory management unit of the USB module needs 3 clock cycles for an
read access to the setup token memory, but a CPU access to the XBUS takes 2 CPU
cycles (= 1 machine cycle), one 1 wait state has to be programmed to read the setup
token. (compare XBCON3 programming in Table 6-7 )
In order to ensure correct access of the on-chip XBUS peripheral groups, the registers
XADRSx must be set to the values shown in table 6-7 prior to the use of the
corresponding peripherals. See also Figure 25-1.
Table 6-7
6.4.2
Because of compatibility (to C16x) the XBUS peripheral groups can be separately se-
lected for being visible by means of corresponding selection bits in the XPERCON reg-
ister. If not selected and therefore not enabled (not activated with XPERCON bit), the
peripheral’s address space including SFR addresses and port pins are not occupied by
the peripheral, thus the peripheral is not visible and not available.
(E)SFR
XADRS1
XADRS2
XADRS3
XADRS4
XBCON1
XBCON2
XBCON3
XBCON4
XBUS Peripheral Configuration Block
ADRSx and XBCONx values to be programmed
Value
0DF0
0DE0
0DD0
0E04
04BF
1437
043F
043E
04BF
H
H
H
H
H
H
H
H
H
( for setup token read only (for details refer to Chapter 22)
80
Central Processor Unit
PSB 21473
2003-03-31
INCA-D