PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 49

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

The on-chip peripheral units of the INCA-D work nearly independent of the CPU. Data
and control information is interchanged between the CPU and these peripherals via
Special Function Registers (SFRs). Whenever peripherals need a non-deterministic
CPU action, an on-chip Interrupt Controller compares all pending peripheral service
requests against each other and prioritizes one of them. If the priority of the current CPU
operation is lower than the priority of the selected peripheral request, an interrupt will
occur.
A set of Special Function Registers is dedicated to the functions of the CPU core:
6.1
The instruction pipeline of the INCA-D partitiones instruction processing into four stages
of which each one has its individual task:
1st –>FETCH:
In this stage the instruction selected by the Instruction Pointer (IP) and the Code
Segment Pointer (CSP) is fetched from either the internal ROM (bootstrap loader),
internal RAM, or external memory.
2nd –>DECODE:
In this stage the instructions are decoded and, if required, the operand addresses are
calculated and the respective operands are fetched. For all instructions, which implicitly
access the system stack, the SP register is either decremented or incremented, as
specified. For branch instructions the Instruction Pointer and the Code Segment Pointer
are updated with the desired branch target address (provided that the branch is taken).
3rd –>EXECUTE:
In this stage an operation is performed on the previously fetched operands in the ALU.
Additionally, the condition flags in the PSW register are updated as specified by the
instruction. All explicit writes to the SFR memory space and all auto-increment or auto-
decrement writes to GPRs used as indirect address pointers are performed during the
execute stage of an instruction, too.
Data Sheet
General System Configuration: SYSCON (RP0H)
CPU Status Indication and Control: PSW
Code Access Control: IP, CSP
Data Paging Control: DPP0, DPP1, DPP2, DPP3
GPRs Access Control: CP
System Stack Access Control: SP, STKUN, STKOV
Multiply and Divide Support: MDL, MDH, MDC
ALU Constants Support: ZEROS, ONES
Instruction Pipelining
49
Central Processor Unit
PSB 21473
2003-03-31
INCA-D