PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 320

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
17.5.1.4 MASKH - Mask Register HDLC
Value after reset: FC
MASKH
Each interrupt source in the ISTAH register can be selectively masked by setting to ’1’
the corresponding bit in MASK. Masked interrupt status bits are not indicated when
ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
17.5.1.5 STAR - Status Register
Value after reset: 40
STAR
XDOV
More than 16/32 bytes have been written in one pool of the XFIFO, i.e. data has been
overwritten.
XFW
Data can be written in the XFIFO. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI
The HDLC receiver is active when RACI = ’1’. This bit may be polled. The RACI bit is set
active after a begin flag has been received and is reset after receiving an abort
sequence.
XACI
The HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The XACI-bit is
active when an XTF-command is issued and the frame has not been completely
transmitted.
XDOV XFW
7
7
RME
... Transmit Data Overflow
... Transmit FIFO Write Enable
... Receiver Active Indication
... Transmitter Active Indication
RPF
H
H
RFO
0
IOM-2 Handler, TIC/CI Handler and HDLC Controller
XPR
0
320
RACI
XMR
XDU
0
XACI
0
0
0
0
0
PSB 21473
2003-03-31
WR (20
INCA-D
RD (21
H
H
)
)