PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 599

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
System Reset
24.7
Ports and External Bus Configuration during Reset
During the internal reset sequence all of the INCA-D's port pins are configured as inputs
by clearing the associated direction registers.
Most of the parallel port lines, i.e including the memory interface, are internally pulled up
to HIGH per default.(For details refer to Chapter 9)
This ensures that the INCA-D and external devices will not try to drive the same pin to
different levels, pin ALE is held low through an internal pulldown, and pins RD and WR
are held high through internal pullups. Also the pins selected for CS output will be pulled
high.
The registers SYSCON and BUSCON0 are initialized according to the configuration
selected via PORT0 as well as the start-up configuration pins at P0L are initializes
according to their reset values.
For an external start:
• the Bus Type field (BTYP) in register BUSCON0 is initialized according to P0L.7 and
P0L.6
• bit BUSACT0 in register BUSCON0 is set to ‘1’
• bit ALECTL0 in register BUSCON0 is set to ‘1’
• bit BYTDIS in register SYSCON is set according to the data bus width
The other bits of register BUSCON0, and the other BUSCON registers are cleared. This
default initialization selects the slowest possible external accesses using the configured
bus type.
When the internal reset has completed, the configuration of PORT0, PORT1, Port 4, Port
6 and of the BHE signal (High Byte Enable, alternate function of P3.12) depends on the
bus type which was selected during reset, i.e. PORT0 (and PORT1) will operate in the
selected bus mode. Port 4 will output the selected number of segment address lines (all
zero after reset) and Port 6 will drive the selected number of CS lines (CS0 will be ‘0’,
while the other active CS line will be ‘1’). When no memory accesses above 64 K are to
be performed, segmentation may be disabled.
When the on-chip bootstrap loader was activated during reset, pin TxD0 (alternate
function of P3.10) will be switched to output mode after the reception of the zero byte.
Application-Specific Initialization Routine
After the internal reset condition is removed the INCA-D fetches the first instruction from
location 00’0000
, which is the first vector in the trap/interrupt vector table, the reset
H
vector. 4 words (locations 00’0000
through 00’0007
) are provided in this table to start
H
H
the initialization after reset. As a rule, this location holds a branch instruction to the actual
initialization routine that may be located anywhere in the address space.
Data Sheet
599
2003-03-31