PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 285

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
IOM-2 Handler, TIC/CI Handler and HDLC Controller
In case the COUNT field of a particular PEC channel control register (PECCx), which is
decremented by one after every transfer, reaches ’00
’ (COUNT defines implicitely the
H
size of the buffer where the transferred data has been stored), the interrupt request is
not cleared as it’s done when COUNT is not ’00
’. Thus the corresponding regular
H
interrupt service routine is called to reinitialize the buffer.
This means also that no PEC transfers with lower interrupt priority will occur if the PEC
channel with higher priority reaches COUNT = 0.
The software has to ensure that servicing all used IOM data transfer interrupts (up to
eight) has to be done within 100µs.
In case all pending interrupts (i.e. PEC transfers) are not completed before the next
frame starts (within 100µs), data access to/from the next frame does not take place and
the interrupt request bit ITRFRIR of the control register ITR_CR is set. No data is written
to and no data is taken from the next frame.
An example is shown in Figure 17-12. ITR_MSK1 is set to receive data from DD at
timeslots B1, B2 and IC1 (in figure indicated with "Mask 1"). ITR_MSK2 is set to transmit
data to DU at TS B1. ITR_MSK3 is set to transmit data to DU at TS B2 and ITR_MSK4
is set to transmit data to DU at TS IC1. After FSC, the mask bits of all ITR_MSKx
registers are checked. Each 1 will generate an interrupt of the corresponding interrupt
line IOMTRAxINT.
After the interrupt has been serviced by PEC transfers, the address for the buffer
registers are incremented and the mask bits are shifted, so that the bits for the next
timeslot are evaluated. Again, if at least one bit was set to 1, the corresponding interrupt
is generated and the access to the data register ITRDU or ITRDD has to occur.
Data Sheet
285
2003-03-31