PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 67

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

The Multiply/Divide High Register MDH
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit
addressable register represents the high order 16 bits of the 32-bit result. For long
divisions, the MDH register must be loaded with the high order 16 bits of the 32-bit
dividend before the division is started. After any division, register MDH represents the
16-bit remainder.
MDH (FE0C
Bit
mdh
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'.
When a multiplication or division is interrupted before its completion and when a new
multiply or divide operation is to be performed within the interrupt service routine, register
MDH must be saved along with registers MDL and MDC to avoid erroneous results.
A detailed description of how to use the MDH register for programming multiply and
divide algorithms can be found in chapter “System Programming”.
The Multiply/Divide Low Register MDL
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit
addressable register represents the low order 16 bits of the 32-bit result. For long
divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit
dividend before the division is started. After any division, register MDL represents the 16-
bit quotient.
MDL (FE0E
Data Sheet
15
15
14
14
H
H
13
13
/ 07
/ 06
Function
Specifies the high order 16 bits of the 32-bit multiply and divide register MD.
H
H
)
)
12
12
11
11
10
10
9
9
8
8
mdh
SFR
SFR
rw
mdl
rw
67
7
7
6
6
5
5
4
4
Central Processor Unit
3
3
Reset Value: 0000
Reset Value: 0000
2
2
PSB 21473
1
1
2003-03-31
INCA-D
0
0
H
H