PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 57

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

CPU Interrupt Status (IEN, ILVL)
The Interrupt Enable bit allows to globally enable (IEN=’1’) or disable (IEN=’0’) interrupts.
The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity.
The interrupt level is updated by hardware upon entry into an interrupt service routine,
but it can also be modified via software to prevent other interrupts from being
acknowledged. In case an interrupt level '15' has been assigned to the CPU, it has the
highest possible priority, and thus the current CPU operation cannot be interrupted
except by hardware traps or external non-maskable interrupts. For details please refer
to chapter “Interrupt and Trap Functions”.
After reset all interrupts are globally disabled, and the lowest priority (ILVL=0) is
assigned to the initial CPU activity.
The Instruction Pointer IP
This register determines the 16-bit intra-segment address of the currently fetched
instruction within the code segment selected by the CSP register. The IP register is not
mapped into the INCA-D's address space, and thus it is not directly accessable by the
programmer. The IP can, however, be modified indirectly via the stack by means of a
return instruction.
The IP register is implicitly updated by the CPU for branch instructions and after
instruction fetch operations.
IP (---- / --)
Bit
ip
The Code Segment Pointer CSP
This non-bit addressable register selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up to 256 segments
of 64 KBytes each, while the upper 8 bits are reserved for future use.
Data Sheet
15
14
13
Function
Specifies the intra segment offset, from where the current instruction is to be
fetched. IP refers to the current segment <SEGNR>.
12
11
10
9
8
rw
---
ip
57
7
6
5
4
Central Processor Unit
3
Reset Value: 0000
2
PSB 21473
1
2003-03-31
INCA-D
0
H