PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 293

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively. For CIR1 no FIFO is available. The actual code
of the received C/I channel 1 is always stored in CIR1.
Please refer to Figure 8-3 for information about the further processing of the CIC
interrupt.
The direction of the CI0 and CI1 handler are determined by the IOM frame arbiter IFA
and programmable with register DCI_CR (address offset 53
17.2.4
The TIC bus is implemented to organize the access to the layer-1 functions and to the
D-channel from up to 7 D-channels HDLC controllers (see Figure 17-15). The arbitration
mechanism must be activated by setting the MODEH.DIM2-0(2:0) signals to 00x.
•
Figure 17-15 Applications of TIC Bus in IOM-2 Bus Configuration
The arbitration mechanism is implemented in the last octet in IOM channel 2 of the IOM-
2 interface. An access request to the TIC bus may either be generated by software or by
the D-channel HDLC controller (transmission of an HDLC frame in the D-channel). A
software access request to the bus is effected by setting the BAC bit (CIX0 register) to
’1’.
Data Sheet
D-channel
D-HDLC(7)
D-HDLC(2)
D-HDLC(1)
control
TIC Bus Handler - Functional Description
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.
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TIC-Bus
on IOM-2
IOM-2 Handler, TIC/CI Handler and HDLC Controller
Transceiver
293
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Device
PSB 21473
macro_9
2003-03-31
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