PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 588

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
For this purpose, the following peripherals which are connected to the PD-bus or to the
XBUS (refer to Figure 3-1 ), ie. SSC0, SSC1, ASC , GPT12 and PIDD have a clock
control register.
Note: The
The clock control registers are called modCLC where mod is substituted by the
corresponding peripheral name, e.g. SSC, ASC or GPT12. With this registers, two
modes can be selected for each peripheral:
Run mode
The peripheral works as expected.
Clock Disable Mode / OCDS Suspend Mode
In case the clock of the peripheral shall be disabled, any pending read and write access
is finished before the actually peripherla gets disabled. then, no write access is possible
as long as clock is disabled. A read to any register returns the register value. However,
each read during disabled clock is non-destructive, i.e., no action is issued upon a read.
The peripheral SSC may serve as an example for this. After transmission, the receive
buffer must be read to avoid getting a receive error with the next transmission. If however
the SSC clock is disabled after a transmission, and the receive buffer is read after having
disabled the ssc clock, then the peripheral does not notice this read and issues an
receive error with the next transmission.
The addresses of the modCLC registers are listed in the dedicated peripheral chapter.
CLK_CONF.USB_DIS to ’1’ and DCR_UCLK to ’0’. For further details refer to
Chapter 22.6
two
clocks
of
the
USB
588
module
can
be
Power Reduction Modes
disabled
PSB 21473
by
2003-03-31
INCA-D
setting