PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 41

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Note: Byte units forming a single word or a double word must always be stored within
5.1
The INCA-D includes an internal ROM for bootstrap loader functionality only. Therefore,
there is no internal ROM available for customized program code storage.
The BSL mechanism may be used for standard system startup as well as only for special
occasions like system maintenance (firmware update) or end-of-line programming or
testing
The INCA-D enters BSL mode, if pin P0L.4 is sampled low at the end of a hardware reset
(See Chapter 24.6). After entering BSL mode and the respective internal initialization
the INCA-D scans the RXD0 line to receive a zero byte, ie. one start bit, eight ‘0’ data
bits and one stop bit. From the duration of this zero byte it calculates the corresponding
baudrate factor with respect to the current CPU clock, initializes the serial interface ASC
accordingly and switches pin TxD0 to output.
In order to execute a program in normal mode, the BSL mode has to be terminated first.
The INCA-D exits BSL mode upon software reset (ignores the level on P0L.4) or a
hardware reset (P0L.4 must be high then). After reset the INCA-D will start executing
from location 00’0000
5.2
The INCA-D provides 4 KBytes of On Chip XRAM. The XRAM is mapped on data page
3 from address 00’E000
5.3
The RAM/SFR area is located within data page 3 and provides access to the internal DP-
RAM (IRAM, organized as X*16) and to two 512 Byte blocks of Special Function
Registers (SFRs). The INCA-D provides 2 KBytes of IRAM, see Figure 5-2.
The IRAM serves for several purposes:
• System Stack (programmable size)
• General Purpose Register Banks (GPRs)
• Source and destination pointers for the Peripheral Event Controller (PEC)
• Variable and other data storage, or
• Code storage.
Data Sheet
the same physical (internal, external, ROM, RAM) and organizational (page,
segment) memory area.
Internal ROM (Bootstrap Loader)
On Chip XRAM
Internal Dual-Port-RAM and SFR Area
H
of the external memory.
H
to 00’EFFF
H
as shown in Figure 5-2.
41
Memory Organization
PSB 21473
2003-03-31
INCA-D