PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 79

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Bit
BSWCx
RDYENx
The smallest possible adress range, which is covered with respect to the XADRSx
register, is 256 bytes. For a better utilization of that memory , the address ranges are in
two cases shared by some XBUS peripherals as described in the table below.
After reset, no address selection register is selected; thus the default address range is
enabled and controlled with BUSCON0 and additionally the chip select output CS0 is
activated (as in standard C16x architecture). In order to use the on-chip XBUS
peripherals , the XADRSx and XBCONx registers must be programmed in a certain way.
The XBUS peripherals correspond to the register pairs XADRSx and XBCONx as
follows:
Table 6-6
All XADRSx/ADDRSELx registers as well as XBCONx/BUSCONx registers are user
programmable SFR registers. All BUSCONx registers are mapped into the
bitaddressable SFR memory space, all XBCONx registers are located in the
bitaddressable ESFR memory space. Although they are free programmable,
programming should be performed during the initialisation phase before the first
accesses are controlled with XBCONx or BUSCONx.
Wait states of IOM2 block
Since the IOM2 block contains modules which have wide variations in their uC access
times, wait states assignment for the different blocks is dynamic. To implement this
dynamic wait state assignment scheme the IOM2 access by the uC is implemented by
Data Sheet
Group number
1
2
3
4
XBUS peripherals groups
Function
BUSCON Switch Control
’0’: Standard switch of bustype (switch of XBCON)
’1’: A bus wait state (Tri-state cycle) is included after execution of last old-
bustype cycle and before the first new-bustype cycle after switch of XBCON or
BUSCON; the BSWC bit is indicated in the old-bustype XBCON/BUSCON.
READY Enable
’0’: The bus cycle length is controlled by the bus controller using MCTC
’1’: The bus cycle length is controlled by the peripheral using READY
IOM handler, HDLC controller,
corresonding peripherals
Transceiver, CI Handler
PIDD, TSF, I2C
XRAM
USB
79
registers
XBCON1 & XADRS1
XBCON2 & XADRS2
XBCON3 & XADRS3
XBCON4 & XADRS4
Central Processor Unit
PSB 21473
2003-03-31
INCA-D