PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 593

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

24.1
The INCA-D differs and indicates the following reset types:
•:
1)
Table 24-1
The duration of 2048 TCL is determined by the internal reset sequence (see below) and
by the necessary sampling time for the startup configuration on port P0.
External Hardware Reset
The INCA-D provides spike suppression for RSTIN pin with an input filter; input signals
shorter than 10ns are suppressed, detection is guaranteed for minimum 150ns reset
signals. The filtered and stable HW reset signal is buffered and distributed to the core
and to the other modules including the pads (signal RST). This internal system reset
signal uses directly the filtered, but asynchronous RSTIN signal for its activation. Its
trailing edge (deactivation) is determined either
– by the synchronized trailing edge of the RSTIN input (hardware reset), or
– by termination of the reset sequence (see below), if still running when RSTIN is
– by termination of the internal lengthening condition, e.g. osc/PLL stabilisation time
With deactivation of the internal RST signal, program execution is started in the core.
Three different kinds of external hardware resets are considered:
– Power-on Reset
– Long Hardware Reset
Data Sheet
Minimum time of a short HW reset SHWR for safe latching
deactivated, or
(see below).
A complete power-on reset requires an active RSTIN time until a stable clock signal
is available. Depending on the oscillation frequency the on-chip oscillator needs about
2...50 ms to stabilize.
A long hardware reset requires an active RSTIN time longer than the duration of the
internal reset sequence. The duration of the internal reset sequence is 2048 TCL.
After the internal reset sequence has been completed, the RSTIN input is sampled.
As long as the reset input is still active the internal reset condition is prolonged.
Watchdog Timer Reset
Short Hardware Reset
Long Hardware Reset
Power-on Reset
Software Reset
Reset Type
Reset Types
Reset Types and Reset Conditions
Short-cut
SHWR
WDTR
LHWR
PONR
SWR
593
16 TCL
t
RSTIN
SRST command
WDT overflow
1)
Condition
Power-on
< t
> 2048 TCL
RSTIN
System Reset
PSB 21473
2048 TCL
2003-03-31
INCA-D