PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 205

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
General Purpose Timer Unit
14.2
Functional Description of Timer Block 2
Timer block 2 includes the two timers T5 (referred to as the auxiliary timer) and T6
(referred to as the core timer), and the 16-bit capture/reload register CAPREL.
Each timer has an input line (TxIN) associated with it which serves as the gate control in
gated timer mode, or as the count input in counter mode. The count direction (Up / Down)
may be programmed via software or may be dynamically altered by a signal at an
external control input line. An overflow/underflow of core timer T6 is indicated by the
output toggle latch T6OTL whose state may be output on related line T6OUT and on line
T6OFL. The auxiliary timer T6 may be reloaded with the contents of CAPREL.
The toggle bit also supports the concatenation of T6 with auxiliary timer T5, while
concatenation of T6 with other timers is provided through line T6OFL. Triggered by an
external signal, the contents of T5 can be captured into register CAPREL, and T5 may
optionally be cleared. Both timer T6 and T5 can count up or down, and the current timer
value can be read or modified by the CPU in the non-bitaddressable SFRs T5 and T6.
T6OFL
Figure 14-15 Structure of Timer Block 2
Data Sheet
205
2003-03-31

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