PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 353

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
Line Transceiver
External Layer-1 Statemachine
Instead of using the integrated layer-1 statemachine it is also possible to implement the
layer-1 statemachine completely in software.
The internal layer-1 statemachine can be disabled by setting the L1SW bit in the
TR_CONF0 register to ’1’.
The transmitter is completely under control of the microcontroller via register TR_CMD.
The status of the receiver is stored in register TR_STA and has to be evaluated by the
microcontroller. This register is updated continuously. If not masked a RIC interrupt is
generated by any change of the register contents. The interrupt is cleared after a read
access to this register.
Reset States
An active signal on the reset pin RSTIN brings the transceiver state machine to the reset
state. The function of this reset event is identical to the C/I code RES concerning the
state machine.
C/I Codes in Reset State
In the reset state the C/I code 0001 (RES) is valid. This state is entered either with a
hardware reset ( RSTIN) or with the C/I code RES.
18.4.1
State Machine
Figure 18-5 shows the state transition diagram of the INCA-D state machine.
18.4.1.1 States
Reset, Pending Deactivation
State after reset or deactivation from the line interface by info 0. Note that no activation
from the terminal side is possible starting from this state. A ‘DI’-command has to be
issued to enter the state ’Deactivated’.
Deactivated State
The lineinterface is deactivated and the clocks are deactivated 500 µs after entering this
state and receiveing info 0 if the pin oscgo is set to “0“. Activation is possible from the
line interface and from the IBUS interface.
Data Sheet
353
2003-03-31

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