PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 521

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
USB Module
the CPU must write the address to SFR ADROFFn and read/write the data byte from/to
register USBVALn.
Sequential Access
In sequential access mode the CPU accesses the data register USBVALn continuously
without setting the address of the next USB memory buffer location. This is done
automatically if bit INCE (increment enable) in the related SFR EPBCRn is set. After a
specific number of CPU accesses (as done in SFR EPLENn), the buffer has been read/
written by the CPU and is empty/full. Setting of bit DONE in software, manually or
automatically, marks the USB buffer ready.
22.4.2
Single Buffer Mode
In single buffer mode the USB and the CPU share one common USB memory page. The
active buffer page can be either page 0 or page 1. Back-to-back transfers are not
possible in this mode. Easy data storage and controlling can be achieved in this mode.
E.g. a once created data set for an interrupt endpoint can be stored permanently in USB
memory. As a result, an additional memory space for data storage is no longer needed.
22.4.2.1 USB Write Access
Figure 22-7 shows the basic flowchart of a USB write access to one USB memory buffer
in single buffer mode.
Data Sheet
521
2003-03-31

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